Tegra 4, same as Tegra 3, requires configuration of CPU and CORE voltages in the SPL stage to boot properly. Expose function to be able perform this configuration in the SPL section of the device board.
Tested-by: Svyatoslav Ryhel clamor95@gmail.com # ASUS TF701T Signed-off-by: Svyatoslav Ryhel clamor95@gmail.com --- arch/arm/mach-tegra/tegra114/cpu.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 62c1053630..7d8f080c31 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -13,9 +13,13 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> +#include <asm/arch-tegra/tegra_i2c.h> #include <linux/delay.h> #include "../cpu.h"
+/* In case this function is not defined */ +__weak void pmic_enable_cpu_vdd(void) {} + /* Tegra114-specific CPU init code */ static void enable_cpu_power_rail(void) { @@ -254,6 +258,7 @@ void start_cpu(u32 reset_vector)
/* Enable VDD_CPU */ enable_cpu_power_rail(); + pmic_enable_cpu_vdd();
/* Get the CPU(s) running */ enable_cpu_clocks();