Burch, John T. schrieb:
Code is relocated from flash to RAM in cpu/mips/start.S/relocate_code(). After the code is moved a comment in the code says, "If caches were enabled, we would have to flush them here." Based on code in the same file, the caches are enabled - and I agree that the data cache needs to be flushed, (and instruction cached invalidated to be safe) but it isn't. Is there a reason it's not?
Also, flush_cache() is not implemented in cpu/mips/cpu.c. This function appears to be required by cmd_net.c/netboot_common(). Is there a reason flush_cache() is not implemented?
I ask because I'm seeing unexplained code behavior that goes away if I don't enable the caches.
Hi, the reason why the cache is not flushed, is that mips_cache_lock(stack pointer) (or so) is called before. This locks the whole data cache beginning from the stack pointer. Any other access to other addresses will not get into dcache, because the dcache lines are locked against replacing. See MIPS spec. Unfortunately the cache locking don't have to be implemented for MIPS 32 4Kc cpus. So the code i think has to be improved. I've implemented a fluch_cache routine to avoid the false behaviour, because the bcm47xx in my case doesn't support it (as it seems for me). On the other side icache don't has to be flushed before relocating, because the start code runs uncached from KSEG1. So my thoughts :)
Anton