It has been a while ago when I had to do something with an intel Arria-10. At that time the support was a bit troublesome.
Some of the issues faced:
U-Boot 2nd stage requires SDRAM to run. The ARRIA-10 DDR controller for the HPS requires at least the peripheral part of the FPGA to be configured. Configuring of the (peripheral part) of FPGA consequently has to be done from the SPL to make SDRAM available. Peripheral and core part of the FPGA must come from the same build.
As a consequence, selecting the FPGA binary to load is not possible from u-boot scripting. Having multiple boot options, failsafe boot, recovery, which are normally possible with u-boot scripting are not possible due to the FPGA constraint to the SPL.
How is the status with respect to those issues ? Have any additions or improvements been made since approx. 2 years ago ? I also wonder how other Arria-10 users deal with this, 'in field' updating the FPGA becomes now just as risky as updating the bootloader (which we by default avoid).
Of course, there possible solutions by modifying the SPL, but I prefer not to re-invent the wheel in case there are other solutions.
Any suggestions are appreciated,
Marcel