Hi,
Please ignore this patch. I will send this as part of another patch series.
Thanks, Ashok
-----Original Message----- From: Ashok Reddy Soma ashok.reddy.soma@xilinx.com Sent: Wednesday, July 20, 2022 3:36 PM To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com; Simek, Michal michal.simek@amd.com; git@xilinx.com; git (AMD-Xilinx) git@amd.com; Reddy, T Karthik t.karthik.reddy@amd.com; Ashok Reddy Soma ashok.reddy.soma@xilinx.com Subject: [PATCH] spi: cadence_ospi_versal: Reset ospi controller using reset driver api's
From: T Karthik Reddy t.karthik.reddy@amd.com
Add a new function to reset the ospi controller. Use reset_assert, reset_deassert api's to reset the ospi controller. In mini U-Boot case as ZYNQMP_FIRMWARE config is disabled, reset the controller directly using register writes.
Signed-off-by: T Karthik Reddy t.karthik.reddy@amd.com Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@xilinx.com ---
arch/arm/mach-versal/include/mach/hardware.h | 1 + drivers/spi/cadence_ospi_versal.c | 29 ++++++++++++++++++++ drivers/spi/cadence_qspi.h | 1 + 3 files changed, 31 insertions(+)
diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 000af974e8..429765234f 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -61,6 +61,7 @@ struct rpu_regs { #define VERSAL_SLCR_BASEADDR 0xF1060000 #define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504) #define VERSAL_OSPI_LINEAR_MODE BIT(1) +#define VERSAL_OSPI_CTRL_RST (VERSAL_CRP_BASEADDR + 0x304)
struct crp_regs { u32 reserved0[128]; diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 52bcad053f..a9c5daff20 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -127,6 +127,35 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat) return 0; }
+int cadence_spi_versal_ctrl_reset(struct cadence_spi_priv *priv) { + int ret; + + if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) { + /* Assert ospi controller */ + ret = reset_assert(priv->resets->resets); + if (ret) + return ret; + + udelay(10); + + /* Deassert ospi controller */ + ret = reset_deassert(priv->resets->resets); + if (ret) + return ret; + } else { + /* Assert ospi controller */ + setbits_le32((u32 *)VERSAL_OSPI_CTRL_RST, 1); + + udelay(10); + + /* Deassert ospi controller */ + clrbits_le32((u32 *)VERSAL_OSPI_CTRL_RST, 1); + } + + return 0; +} + #if defined(CONFIG_DM_GPIO) int cadence_spi_versal_flash_reset(struct udevice *dev) { diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index c8d16bb0e4..3f5f45282d 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -285,5 +285,6 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat); int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); int cadence_qspi_versal_flash_reset(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable); +int cadence_spi_versal_ctrl_reset(struct cadence_spi_priv *priv);
#endif /* __CADENCE_QSPI_H__ */ -- 2.17.1