Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI stack. This change showed a few different problems on TI platforms (where our cacheline size is 64 not 32). First, the dcache_off call that ehci-omap had been doing was now not happening soon enough to paper over the cache issues. This call is removed in patch 1. Second, when we have dcache support compiled in but turned off via 'dcache off' the cache routines spam the console about alignment issues when a cache flush is attempted. This is a problem in that it makes operations extremely slow (as we're spending all our time spitting messages to console). The second patch makes the flush routines return when the dcache is off. The last two patches deal with the same problem, for EHCI and for MUSB. The USB spec says that 32 bytes is the minimum alignment but we need larger alignment when the cache is larger. Note that we can't use MAX() here as gcc doesn't allow that expansion inside of align(..).
Tested on omap3_beagle (which was previously broken) and a MAKEALL -a arm looks good too.