On 1/28/22 14:47, Alexandre Ghiti wrote:
The following description is copied from the equivalent patch for the Linux Kernel proposed by Aurelien Jarno:
From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure:
arch/riscv/cpu/mtrap.S: Assembler messages: arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
I tried to build qemu-riscv64_smode_defconfig. With your patch I get
arch/riscv/cpu/cpu.c: Assembler messages: arch/riscv/cpu/cpu.c:94: Error: unrecognized opcode `csrs sstatus,a5' arch/riscv/cpu/cpu.c:95: Error: unrecognized opcode `csrw 0x003,0'
The build flag used is -march=rv64imac.
My toolchain is: binutils 2.37.90.20220126-0ubuntu1 riscv64-linux-gnu-gcc (Ubuntu 10.3.0-8ubuntu1) 10.3.0
This GCC does not support _zicsr_zifencei: cc1: error: ‘-march=rv64imac_zicsr_zifencei’: unsupported ISA subset ‘z
Could it be that the GCC is too old for the new binutils? When was the z subset added to GCC?
What about the device trees:
arch/riscv/dts/fu540-c000.dtsi:32: riscv,isa = "rv64imac";
arch/riscv/dts/fu740-c000.dtsi:34: riscv,isa = "rv64imac";
arch/riscv/dts/microchip-mpfs.dtsi:28: riscv,isa = "rv64imac";
Best regards
Heinrich
Signed-off-by: Alexandre Ghiti alexandre.ghiti@canonical.com
arch/riscv/Makefile | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0b80eb8d86..53d1194ffb 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif
-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
+# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) +ifeq ($(toolchain-need-zicsr-zifencei),y)
- RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
+endif
+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL)
PLATFORM_CPPFLAGS += $(ARCH_FLAGS)