Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-keystone/clock-k2e.c | 6 ------ arch/arm/mach-keystone/clock-k2hk.c | 8 -------- arch/arm/mach-keystone/clock-k2l.c | 7 ------- arch/arm/mach-keystone/clock.c | 8 ++++++++ arch/arm/mach-keystone/include/mach/clock-k2e.h | 8 -------- arch/arm/mach-keystone/include/mach/clock-k2hk.h | 9 --------- arch/arm/mach-keystone/include/mach/clock-k2l.h | 8 -------- arch/arm/mach-keystone/include/mach/clock.h | 13 ++++++++++++- arch/arm/mach-keystone/include/mach/hardware-k2hk.h | 4 ---- arch/arm/mach-keystone/include/mach/hardware.h | 2 ++ 10 files changed, 22 insertions(+), 51 deletions(-)
diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c index 42092e1..b23d2a5 100644 --- a/arch/arm/mach-keystone/clock-k2e.c +++ b/arch/arm/mach-keystone/clock-k2e.c @@ -11,12 +11,6 @@ #include <asm/arch/clock.h> #include <asm/arch/clock_defs.h>
-const struct keystone_pll_regs keystone_pll_regs[] = { - [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, - [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, - [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, -}; - /** * pll_freq_get - get pll frequency * Fout = Fref * NF(mult) / NR(prediv) / OD diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c index 96a9f72..2e36891 100644 --- a/arch/arm/mach-keystone/clock-k2hk.c +++ b/arch/arm/mach-keystone/clock-k2hk.c @@ -11,14 +11,6 @@ #include <asm/arch/clock.h> #include <asm/arch/clock_defs.h>
-const struct keystone_pll_regs keystone_pll_regs[] = { - [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, - [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, - [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, - [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, - [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, -}; - /** * pll_freq_get - get pll frequency * Fout = Fref * NF(mult) / NR(prediv) / OD diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c index 80c1f51..0bd0fd6 100644 --- a/arch/arm/mach-keystone/clock-k2l.c +++ b/arch/arm/mach-keystone/clock-k2l.c @@ -11,13 +11,6 @@ #include <asm/arch/clock.h> #include <asm/arch/clock_defs.h>
-const struct keystone_pll_regs keystone_pll_regs[] = { - [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, - [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, - [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, - [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, -}; - /** * pll_freq_get - get pll frequency * Fout = Fref * NF(mult) / NR(prediv) / OD diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index cad9ff3..f60a0b8 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -25,6 +25,14 @@ static int speeds[] = { SPD800, };
+const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, + [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, + [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, +}; + static void wait_for_completion(const struct pll_init_data *data) { int i; diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h index 42be2ca..3bde6da 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2e.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h @@ -50,14 +50,6 @@ extern unsigned int external_clk[ext_clk_count];
#define KS2_CLK1_6 sys_clk0_6_clk
-/* PLL identifiers */ -enum pll_type_e { - CORE_PLL, - PASS_PLL, - DDR3_PLL, - TETRIS_PLL, -}; - #define CORE_PLL_800 {CORE_PLL, 16, 1, 2} #define CORE_PLL_850 {CORE_PLL, 17, 1, 2} #define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h index c41210c..366bf0e 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h @@ -55,15 +55,6 @@ extern unsigned int external_clk[ext_clk_count];
#define KS2_CLK1_6 sys_clk0_6_clk
-/* PLL identifiers */ -enum pll_type_e { - CORE_PLL, - PASS_PLL, - TETRIS_PLL, - DDR3A_PLL, - DDR3B_PLL, -}; - #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} #define CORE_PLL_999 {CORE_PLL, 122, 15, 1} diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h index c145a1e..e3f005a 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2l.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h @@ -51,14 +51,6 @@ extern unsigned int external_clk[ext_clk_count];
#define KS2_CLK1_6 sys_clk0_6_clk
-/* PLL identifiers */ -enum pll_type_e { - CORE_PLL, - PASS_PLL, - TETRIS_PLL, - DDR3_PLL, -}; - #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} #define CORE_PLL_1000 {CORE_PLL, 114, 7, 2} diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 2192c0d..dc3c56a 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -24,7 +24,8 @@ #include <asm/arch/clock-k2l.h> #endif
-#define MAIN_PLL CORE_PLL +#define CORE_PLL MAIN_PLL +#define DDR3_PLL DDR3A_PLL
#include <asm/types.h>
@@ -41,6 +42,16 @@ enum { SPD1500, };
+/* PLL identifiers */ +enum { + MAIN_PLL, + TETRIS_PLL, + PASS_PLL, + DDR3A_PLL, + DDR3B_PLL, + MAX_PLL_COUNT, +}; + enum clk_e { CLK_LIST(GENERATE_ENUM) }; diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h index 195c0d3..8c771dc 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h @@ -15,10 +15,6 @@ /* PA SS Registers */ #define KS2_PASS_BASE 0x02000000
-/* PLL control registers */ -#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) -#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) - /* Power and Sleep Controller (PSC) Domains */ #define KS2_LPSC_MOD 0 #define KS2_LPSC_DUMMY1 1 diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 30022db..6d4015c 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -165,6 +165,8 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) #define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) #define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) +#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) +#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) #define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) #define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)