Hi,
On Sat, Mar 30, 2019 at 9:18 PM Simon Glass sjg@chromium.org wrote:
Hi Urja,
On Fri, 22 Mar 2019 at 13:15, Urja Rannikko urjaman@gmail.com wrote:
This failed and caused a boot failure on c201, and afaik the pins should be setup by the new pinctrl driver.
It should be set up in SPL, if enabled.
I wonder when this code is actually used?
The original code mentioned chainloading so i thought eg. from coreboot, but i mean i thought you should know better than me, see commit fe974716326ce2eee4bcac710ce7ec007919845e. It seemed to also have something to do with the clock driver (which is a thing that has changed in the last 2 years too...).
Signed-off-by: Urja Rannikko urjaman@gmail.com
arch/arm/mach-rockchip/rk3288-board.c | 12 ------------ 1 file changed, 12 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org