Hi,
On Tue, Aug 19, 2014 at 03:54:50AM +0100, Alison Wang wrote:
From: Wang Huan b18965@freescale.com
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability.
Signed-off-by: Alison Wang alison.wang@freescale.com Signed-off-by: Jason Jin jason.jin@freescale.com Signed-off-by: Jingchang Lu jingchang.lu@freescale.com Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com
Change log: v5: No change. v4: No change. v3: Fix checkpatch errors. v2: Add serdes support. Update DDR frequency and data rate information. Fix overflow condition error for the timer.
[...]
+int timer_init(void) +{
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;unsigned long ctrl, val, freq;/* Enable System Counter */writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);freq = GENERIC_TIMER_CLK;asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
Is CNTFRQ initialised for both CPUs?
If the CPUs are booted at PL1 rather than PL2, is CNTVOFF initialised to the same value on both CPUs?
Thanks, Mark.