On Fri, Apr 12, 2013 at 7:10 AM, TENART Antoine <atenart@adeneo-embedded.com
wrote:
Signed-off-by: Antoine Tenart atenart@adeneo-embedded.com
MAINTAINERS | 4 + arch/arm/include/asm/arch-am33xx/spl.h | 9 + board/ti/ti816x/Makefile | 48 ++ board/ti/ti816x/evm.c | 866 ++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/ti816x_evm.h | 177 +++++++ 6 files changed, 1105 insertions(+) create mode 100644 board/ti/ti816x/Makefile create mode 100644 board/ti/ti816x/evm.c create mode 100644 include/configs/ti816x_evm.h
diff --git a/MAINTAINERS b/MAINTAINERS index 6b2202c..3aaac7f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -922,6 +922,10 @@ Lucas Stach dev@lynxeye.de
colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core)+Antoine Tenart atenart@adeneo-embedded.com
TI816X ARM ARMV7 (TI816x Soc)Nick Thompson nick.thompson@gefanuc.com
da830evm ARM926EJS (DA830/OMAP-L137)diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 9b5fe9e..d0c1ec9 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -23,6 +23,14 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_SPL_H_
+#if defined(CONFIG_TI816X) +#define BOOT_DEVICE_XIP 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_MMC1 6 +#define BOOT_DEVICE_MMC2 5 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_MMC2_2 0xFF +#else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 #ifdef CONFIG_AM33XX @@ -37,3 +45,4 @@ #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF #endif +#endif diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile new file mode 100644 index 0000000..59128ee --- /dev/null +++ b/board/ti/ti816x/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> +# Antoine Tenart, atenart@adeneo-embedded.com +# +# Based on TI-PSP-04.00.02.14 : +# +# Copyright (C) 2009, Texas Instruments, Incorporated +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation version 2. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(BOARD).o
+COBJS := evm.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS))
+$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))+clean:
rm -f $(OBJS)+distclean: clean
rm -f $(LIB) core *.bak $(obj).depend+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend
+#########################################################################
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c new file mode 100644 index 0000000..bb9d604 --- /dev/null +++ b/board/ti/ti816x/evm.c @@ -0,0 +1,866 @@ +/*
- evm.c
- Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- Antoine Tenart, atenart@adeneo-embedded.com
- Based on TI-PSP-04.00.02.14 :
- Copyright (C) 2009, Texas Instruments, Incorporated
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation version 2.
- This program is distributed "as is" WITHOUT ANY WARRANTY of any
- kind, whether express or implied; without even the implied warranty
- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- */
+#include <common.h> +#include <spl.h> +#include <asm/cache.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h>
+DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_TI816X_DDR3_SW_LEVELING +static void ddr3_sw_levelling(int emif); +#endif
+int board_init(void) +{
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;return 0;+}
+#if defined(CONFIG_SPL_BUILD)
+static struct module_pin_mux mmc_pin_mux[] = {
{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },{ OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },{ OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },{ OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },{ OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },{ OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },{ -1 },+};
+const struct dmm_lisa_map_regs evm_lisa_map_regs = {
.dmm_lisa_map_0 = 0x00000000,.dmm_lisa_map_1 = 0x00000000,.dmm_lisa_map_2 = 0x80640300,.dmm_lisa_map_3 = 0xC0640320,+};
+/*
- Routine: delay
- Description: spinning delay to use before udelay works
- */
+static inline void delay(unsigned long loops) +{
__asm__ volatile ("1:\n" "subs %0, %1, #1\n""bne 1b" : "=r" (loops) : "0"(loops));+}
+/* assume delay is aprox at least 1us */ +void ddr_delay(int d) +{
int i;/** read a control module register.* this is a bit more delay and cannot be optimized by the compiler* assuming one read takes 200 cycles and A8 is runing 1 GHz* somewhat conservative setting*/for (i = 0; i < 50*d; i++)readl(CONTROL_STATUS);+}
these seem more SOC specific than board specific. Would likely be replicated per board, I'd suggest to move out of board specific file.
+#ifdef CONFIG_TI816X_EVM_DDR3 +/*
- Init DDR3 on TI816X EVM
- */
+static void ddr_init_settings(int emif)
this function is generic to the SOC, move out of board specific file and call with appropriate values or defines
+{
/** DLL Lockdiff DLL_Lockdiff determines effectively is the* threshold internal to the DLL to indicate that the DLL has* lost lock. When this happens the PHY currently issues an* internal reset. The reset value for this is 0x4, which is* insufficient. Set this to 15 (maximum possible - to* prevent this reset. If the reset happens it would cause* the data to be corrupted.*/if (0 == get_cpu_rev()) {writel(0xF, DDRPHY_CONFIG_BASE + 0x028);writel(0xF, DDRPHY_CONFIG_BASE + 0x05C);writel(0xF, DDRPHY_CONFIG_BASE + 0x090);writel(0xF, DDRPHY_CONFIG_BASE + 0x138);writel(0xF, DDRPHY_CONFIG_BASE + 0x1DC);writel(0xF, DDRPHY_CONFIG_BASE + 0x280);writel(0xF, DDRPHY_CONFIG_BASE + 0x324);}/** setup use_rank_delays to 1. This is only necessary when* multiple ranks are in use. Though the EVM does not have* multiple ranks, this is a good value to set.*/writel(1, DDRPHY_CONFIG_BASE + 0x134);writel(1, DDRPHY_CONFIG_BASE + 0x1d8);writel(1, DDRPHY_CONFIG_BASE + 0x27c);writel(1, DDRPHY_CONFIG_BASE + 0x320);/* see ddr_defs.h for invert clock setting and details *//* invert_clk_out cmd0 */writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x02C);/* invert_clk_out cmd0 */writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x060);/* invert_clk_out cmd0 */writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x094);/* with inv clkout: 0x100. no inv clkout: 0x80. See ddr_defs.h *//* cmd0 slave ratio */writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x01C);/* cmd1 slave ratio */writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x050);/* cmd2 slave ratio */writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x084);/* for ddr3 this needs to be set to 1 */writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */writel(0x1, DDRPHY_CONFIG_BASE + 0x104);writel(0x1, DDRPHY_CONFIG_BASE + 0x19C);writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8);writel(0x1, DDRPHY_CONFIG_BASE + 0x240);writel(0x1, DDRPHY_CONFIG_BASE + 0x24C);writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4);writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0);/**** setup the initial levelinihg ratios ****/
typo
/** These are derived from board delays and may be different for* different boards see ddr_defs.h* We are setting the values here for both the ranks, though only* one is in use*//* data0 writelvl init ratio */writel((WR_DQS_RATIO_3 << 10) | WR_DQS_RATIO_3,DDRPHY_CONFIG_BASE + 0x0F0);writel(0x00000, DDRPHY_CONFIG_BASE + 0x0F4);/* data1 writelvl init ratio */writel((WR_DQS_RATIO_2 << 10) | WR_DQS_RATIO_2,DDRPHY_CONFIG_BASE + 0x194);writel(0x00000, DDRPHY_CONFIG_BASE + 0x198);/* data2 writelvl init ratio */writel((WR_DQS_RATIO_1 << 10) | WR_DQS_RATIO_1,DDRPHY_CONFIG_BASE + 0x238);writel(0x00000, DDRPHY_CONFIG_BASE + 0x23c);/* data3 writelvl init ratio */writel((WR_DQS_RATIO_0 << 10) | WR_DQS_RATIO_0,DDRPHY_CONFIG_BASE + 0x2dc);writel(0x00000, DDRPHY_CONFIG_BASE + 0x2e0);/* data0 gatelvl init ratio */writel((RD_GATE_RATIO_3 << 10) | RD_GATE_RATIO_3,DDRPHY_CONFIG_BASE + 0x0FC);writel(0x0, DDRPHY_CONFIG_BASE + 0x100);/* data1 gatelvl init ratio */writel((RD_GATE_RATIO_2 << 10) | RD_GATE_RATIO_2,DDRPHY_CONFIG_BASE + 0x1A0);writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4);/* data2 gatelvl init ratio */writel((RD_GATE_RATIO_1 << 10) | RD_GATE_RATIO_1,DDRPHY_CONFIG_BASE + 0x244);writel(0x0, DDRPHY_CONFIG_BASE + 0x248);/* data3 gatelvl init ratio */writel((RD_GATE_RATIO_0 << 10) | RD_GATE_RATIO_0,DDRPHY_CONFIG_BASE + 0x2E8);writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC);/* cmd0 io config - output impedance of pad */writel(0x5, DDRPHY_CONFIG_BASE + 0x00C);/* cmd0 io clk config - output impedance of pad */writel(0x5, DDRPHY_CONFIG_BASE + 0x010);/* cmd1 io config - output impedance of pad */writel(0x5, DDRPHY_CONFIG_BASE + 0x040);/* cmd1 io clk config - output impedance of pad */writel(0x5, DDRPHY_CONFIG_BASE + 0x044);/* cmd2 io config - output impedance of pad */writel(0x5, DDRPHY_CONFIG_BASE + 0x074);/* cmd2 io clk config - output impedance of pad */writel(0x5, DDRPHY_CONFIG_BASE + 0x078);/* data0 io config - output impedance of pad */writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8);/* data0 io clk config - output impedance of pad */writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC);/* data1 io config - output impedance of pad */writel(0x4, DDRPHY_CONFIG_BASE + 0x14C);/* data1 io clk config - output impedance of pad */writel(0x4, DDRPHY_CONFIG_BASE + 0x150);/* data2 io config - output impedance of pa */writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0);/* data2 io clk config - output impedance of pad */writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4);/* data3 io config - output impedance of pa */writel(0x4, DDRPHY_CONFIG_BASE + 0x294);/* data3 io clk config - output impedance of pad */writel(0x4, DDRPHY_CONFIG_BASE + 0x298);if (get_cpu_rev() == 0) {/* fifo_we_out0 - output impedance of pad */writel(0x5, DDRPHY_CONFIG_BASE + 0x338);/* fifo_we_out1 - output impedance of pad */writel(0x5, DDRPHY_CONFIG_BASE + 0x340);/* fifo_we_in2 - output impedance of pad */writel(0x5, DDRPHY_CONFIG_BASE + 0x348);/* fifo_we_in3 - output impedance of pad */writel(0x5, DDRPHY_CONFIG_BASE + 0x350);}+}
+static void emif4p_init(u32 TIM1, u32 TIM2, u32 TIM3, u32 SDREF, u32 SDCFG,
u32 RL)
again function generic to SOC, move out of board file, applies for a lot of what follows, but I'll stop repeating it :-)
+{
if (USE_EMIF0) {/* Program EMIF0 CFG Registers */writel(TIM1, EMIF4_0_SDRAM_TIM_1);writel(TIM1, EMIF4_0_SDRAM_TIM_1_SHADOW);writel(TIM2, EMIF4_0_SDRAM_TIM_2);writel(TIM2, EMIF4_0_SDRAM_TIM_2_SHADOW);writel(TIM3, EMIF4_0_SDRAM_TIM_3);writel(TIM3, EMIF4_0_SDRAM_TIM_3_SHADOW);writel(SDCFG, EMIF4_0_SDRAM_CONFIG);writel(RL, EMIF4_0_DDR_PHY_CTRL_1);writel(RL, EMIF4_0_DDR_PHY_CTRL_1_SHADOW);/* initially a large refresh period */writel(0x0000613B, EMIF4_0_SDRAM_REF_CTRL);/* trigger initialization */writel(0x1000613B, EMIF4_0_SDRAM_REF_CTRL);writel((0x10000000|EMIF_SDREF), EMIF4_0_SDRAM_REF_CTRL);}if (USE_EMIF1) {/* Program EMIF1 CFG Registers */writel(TIM1, EMIF4_1_SDRAM_TIM_1);writel(TIM1, EMIF4_1_SDRAM_TIM_1_SHADOW);writel(TIM2, EMIF4_1_SDRAM_TIM_2);writel(TIM2, EMIF4_1_SDRAM_TIM_2_SHADOW);writel(TIM3, EMIF4_1_SDRAM_TIM_3);writel(TIM3, EMIF4_1_SDRAM_TIM_3_SHADOW);writel(SDCFG, EMIF4_1_SDRAM_CONFIG);writel(RL, EMIF4_1_DDR_PHY_CTRL_1);writel(RL, EMIF4_1_DDR_PHY_CTRL_1_SHADOW);/* initially a large refresh period */writel(0x0000613B, EMIF4_1_SDRAM_REF_CTRL);/* trigger initialization */writel(0x1000613B, EMIF4_1_SDRAM_REF_CTRL);writel((0x10000000|EMIF_SDREF), EMIF4_1_SDRAM_REF_CTRL);}delay(1000);+#ifdef CONFIG_TI816X_DDR3_SW_LEVELING
ddr3_sw_levelling(0);ddr3_sw_levelling(1);
call levelling code on both interfaces if only one EMIF is being used? make conditional on USE_EMIF1
+#endif +}
+/* needed by config_dmm() */ +void enable_dmm_clocks(void) {};
+static void config_ti816x_sdram_ddr(void)
again SOC specific code to move out of board file
+{
/* Enable the EMIF Firewall clocks */writel(0x2, CM_DEFAULT_FW_CLKCTRL);/* Enable the Power Domain Transition of L3 Fast Domain Peripheral*/
writel(0x2, CM_DEFAULT_L3_FAST_CLKSTCTRL);/* Enable EMIF0 Clock */writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL);/* Enable EMIF1 Clock */writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL);/* Poll for L3_FAST_GCLK & DDR_GCLK are active */while ((readl(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300) != 0x300);/* Poll for Module is functional */while ((readl(CM_DEFAULT_EMIF_0_CLKCTRL)) != 0x2);/* Poll for Module is functional */while ((readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2);if (USE_EMIF0)ddr_init_settings(0);if (USE_EMIF1)ddr_init_settings(1);/* Enable EMIF1 Clock */writel(0x2, CM_DEFAULT_DMM_CLKCTRL);/* Poll for Module is functional */while ((readl(CM_DEFAULT_DMM_CLKCTRL)) != 0x2);/* Program the DMM to for interleaved configuration */config_dmm(&evm_lisa_map_regs);/* Enable Tiled Access */writel(0x80000000, DMM_PAT_BASE_ADDR);emif4p_init(EMIF_TIM1, EMIF_TIM2, EMIF_TIM3, EMIF_SDREF &0xFFFFFFF,
EMIF_SDCFG, EMIF_PHYCFG);+}
+#ifdef CONFIG_TI816X_DDR3_SW_LEVELING +static void ddr3_sw_levelling(int emif) +{
writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));writel(DQS_GATE_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x108));writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x10C));writel(DQS_GATE_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1AC));writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x1B0));writel(DQS_GATE_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x250));writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x254));writel(DQS_GATE_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2F4));writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x2F8));writel(WR_DQS_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x0DC));writel(0x0, (DDRPHY_CONFIG_BASE + 0x0E0));writel(WR_DQS_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x180));writel(0x0, (DDRPHY_CONFIG_BASE + 0x184));writel(WR_DQS_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x224));writel(0x0, (DDRPHY_CONFIG_BASE + 0x228));writel(WR_DQS_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2C8));writel(0x0, (DDRPHY_CONFIG_BASE + 0x2CC));writel(WR_DATA_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x120));writel(0x0, (DDRPHY_CONFIG_BASE + 0x124));writel(WR_DATA_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1C4));writel(0x0, (DDRPHY_CONFIG_BASE + 0x1C8));writel(WR_DATA_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x268));writel(0x0, (DDRPHY_CONFIG_BASE + 0x26C));writel(WR_DATA_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x30C));writel(0x0, (DDRPHY_CONFIG_BASE + 0x310));writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x0C8));writel(0x0, (DDRPHY_CONFIG_BASE + 0x0CC));writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x16C));writel(0x0, (DDRPHY_CONFIG_BASE + 0x170));writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x210));writel(0x0, (DDRPHY_CONFIG_BASE + 0x214));writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x2B4));writel(0x0, (DDRPHY_CONFIG_BASE + 0x2B8));+} +#endif /* CONFIG_TI816X_DDR3_SW_LEVELING */
+#endif /* CONFIG_TI816X_EVM_DDR3 */
+#ifdef CONFIG_TI816X_EVM_DDR2 +static void ddr_init_settings(int emif) +{
/* DLL Lockdiff */if (get_cpu_rev() == 0) {writel(0xF, (DDRPHY_CONFIG_BASE + 0x028));writel(0xF, (DDRPHY_CONFIG_BASE + 0x05C));writel(0xF, (DDRPHY_CONFIG_BASE + 0x090));writel(0xF, (DDRPHY_CONFIG_BASE + 0x138));writel(0xF, (DDRPHY_CONFIG_BASE + 0x1DC));writel(0xF, (DDRPHY_CONFIG_BASE + 0x280));writel(0xF, (DDRPHY_CONFIG_BASE + 0x324));}if (get_cpu_rev() == 1)writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));/* setup rank delays */writel(0x1, (DDRPHY_CONFIG_BASE + 0x134));writel(0x1, (DDRPHY_CONFIG_BASE + 0x1D8));writel(0x1, (DDRPHY_CONFIG_BASE + 0x27C));writel(0x1, (DDRPHY_CONFIG_BASE + 0x320));/* invert_clk_out cmd0 */writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x02C));writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x060));writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x094));/* cmd0 slave ratio */writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x01C));writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x050));writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x084));writel(DQS_GATE_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x108));writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x10C));writel(DQS_GATE_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1AC));writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x1B0));writel(DQS_GATE_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x250));writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x254));writel(DQS_GATE_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2F4));writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x2F8));writel(WR_DQS_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x0DC));writel(0x0, (DDRPHY_CONFIG_BASE + 0x0E0));writel(WR_DQS_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x180));writel(0x0, (DDRPHY_CONFIG_BASE + 0x184));writel(WR_DQS_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x224));writel(0x0, (DDRPHY_CONFIG_BASE + 0x228));writel(WR_DQS_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2C8));writel(0x0, (DDRPHY_CONFIG_BASE + 0x2CC));writel(WR_DATA_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x120));writel(0x0, (DDRPHY_CONFIG_BASE + 0x124));writel(WR_DATA_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1C4));writel(0x0, (DDRPHY_CONFIG_BASE + 0x1C8));writel(WR_DATA_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x268));writel(0x0, (DDRPHY_CONFIG_BASE + 0x26C));writel(WR_DATA_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x30C));writel(0x0, (DDRPHY_CONFIG_BASE + 0x310));writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x0C8));writel(0x0, (DDRPHY_CONFIG_BASE + 0x0CC));writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x16C));writel(0x0, (DDRPHY_CONFIG_BASE + 0x170));writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x210));writel(0x0, (DDRPHY_CONFIG_BASE + 0x214));writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x2B4));writel(0x0, (DDRPHY_CONFIG_BASE + 0x2B8));writel(0x5, (DDRPHY_CONFIG_BASE + 0x00C));writel(0x5, (DDRPHY_CONFIG_BASE + 0x010));writel(0x5, (DDRPHY_CONFIG_BASE + 0x040));writel(0x5, (DDRPHY_CONFIG_BASE + 0x044));writel(0x5, (DDRPHY_CONFIG_BASE + 0x074));writel(0x5, (DDRPHY_CONFIG_BASE + 0x078));writel(0x4, (DDRPHY_CONFIG_BASE + 0x0A8));writel(0x4, (DDRPHY_CONFIG_BASE + 0x0AC));writel(0x4, (DDRPHY_CONFIG_BASE + 0x14C));writel(0x4, (DDRPHY_CONFIG_BASE + 0x150));writel(0x4, (DDRPHY_CONFIG_BASE + 0x1F0));writel(0x4, (DDRPHY_CONFIG_BASE + 0x1F4));writel(0x4, (DDRPHY_CONFIG_BASE + 0x294));writel(0x4, (DDRPHY_CONFIG_BASE + 0x298));if (get_cpu_rev() == 0) {writel(0x5, (DDRPHY_CONFIG_BASE + 0x338));writel(0x5, (DDRPHY_CONFIG_BASE + 0x340));writel(0x5, (DDRPHY_CONFIG_BASE + 0x348));writel(0x5, (DDRPHY_CONFIG_BASE + 0x350));}+}
+static void emif4p_init(u32 TIM1, u32 TIM2, u32 TIM3, u32 SDREF, u32 SDCFG,
u32 RL)+{
/* Program EMIF0 CFG Registers */writel(TIM1, EMIF4_0_SDRAM_TIM_1);writel(TIM1, EMIF4_0_SDRAM_TIM_1_SHADOW);writel(TIM2, EMIF4_0_SDRAM_TIM_2);writel(TIM2, EMIF4_0_SDRAM_TIM_2_SHADOW);writel(TIM3, EMIF4_0_SDRAM_TIM_3);writel(TIM3, EMIF4_0_SDRAM_TIM_3_SHADOW);writel(SDCFG, EMIF4_0_SDRAM_CONFIG);writel(RL, EMIF4_0_DDR_PHY_CTRL_1);writel(RL, EMIF4_0_DDR_PHY_CTRL_1_SHADOW);if (CONFIG_TI816X_TWO_EMIF) {writel(TIM1, EMIF4_1_SDRAM_TIM_1);writel(TIM1, EMIF4_1_SDRAM_TIM_1_SHADOW);writel(TIM2, EMIF4_1_SDRAM_TIM_2);writel(TIM2, EMIF4_1_SDRAM_TIM_2_SHADOW);writel(TIM3, EMIF4_1_SDRAM_TIM_3);writel(TIM3, EMIF4_1_SDRAM_TIM_3_SHADOW);writel(SDCFG, EMIF4_1_SDRAM_CONFIG);writel(RL, EMIF4_1_DDR_PHY_CTRL_1);writel(RL, EMIF4_1_DDR_PHY_CTRL_1_SHADOW);}/* setup a small control period */writel(0x0000613B, EMIF4_0_SDRAM_REF_CTRL);writel(0x1000613B, EMIF4_0_SDRAM_REF_CTRL);writel((0x10000000|SDREF), EMIF4_0_SDRAM_REF_CTRL);if (CONFIG_TI816X_TWO_EMIF) {/* setup a small control period */writel(0x0000613B, EMIF4_1_SDRAM_REF_CTRL);writel(0x1000613B, EMIF4_1_SDRAM_REF_CTRL);writel((0x10000000|SDREF), EMIF4_1_SDRAM_REF_CTRL);}+}
+/* needed by config_dmm() */ +void enable_dmm_clocks(void) {};
+static void config_ti816x_sdram_ddr(void) +{
/* Enable the Power Domain Transition of L3 Fast Domain Peripheral*/
writel(0x2, CM_DEFAULT_L3_FAST_CLKSTCTRL);/* Enable EMIF0 Clock */writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL);/* Enable EMIF1 Clock */writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL);/* Poll for L3_FAST_GCLK & DDR_GCLK are active */while ((readl(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300) != 0x300);/* Poll for Module is functional */while ((readl(CM_DEFAULT_EMIF_0_CLKCTRL)) != 0x2);/* Poll for Module is functional */while ((readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2);ddr_init_settings(0);if (CONFIG_TI816X_TWO_EMIF)ddr_init_settings(1);/* Enable EMIF1 Clock */writel(0x2, CM_DEFAULT_DMM_CLKCTRL);/* Poll for Module is functional */while ((readl(CM_DEFAULT_DMM_CLKCTRL)) != 0x2);/* Program the DMM for interleave setting */config_dmm(&evm_lisa_map_regs);/* Enable Tiled Access */writel(0x80000000, DMM_PAT_BASE_ADDR);emif4p_init(EMIF_TIM1, EMIF_TIM2, EMIF_TIM3, EMIF_SDREF &0xFFFFFFF,
EMIF_SDCFG, EMIF_PHYCFG);+} +#endif
+/*
- TI816X specific functions
- */
+static void main_pll_init_ti816x(u32 sil_index, u32 clk_index) +{
u32 main_pll_ctrl = 0;/** Sequence to be followed:* 1. Put the PLL in bypass mode by setting BIT2 in its ctrl reg* 2. Write the values of N,P in the CTRL reg* 3. Program the freq values, divider values for the requiredoutput
* in the Control module reg* 4. Note: Loading the freq value requires a particular bit to beset
* in the freq reg.* 4. Program the CM divider value in the CM module reg* 5. Enable the PLL by setting the appropriate bit in the CTRLreg of
* the PLL*//* If the registers have been set by the ROM code dont do anything*/
main_pll_ctrl = readl(MAINPLL_CTRL);main_pll_ctrl &= 0xFFFFFFFB;main_pll_ctrl |= 4;writel(main_pll_ctrl, MAINPLL_CTRL);main_pll_ctrl = readl(MAINPLL_CTRL);main_pll_ctrl &= 0xFFFFFFF7;main_pll_ctrl |= 8;writel(main_pll_ctrl, MAINPLL_CTRL);main_pll_ctrl = readl(MAINPLL_CTRL);main_pll_ctrl &= 0xFF;main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);writel(main_pll_ctrl, MAINPLL_CTRL);writel(0x0, MAINPLL_PWD);writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),MAINPLL_FREQ1);writel(((1<<8) | MAIN_MDIV1), MAINPLL_DIV1);writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),MAINPLL_FREQ2);writel(((1<<8) | MAIN_MDIV2), MAINPLL_DIV2);writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),MAINPLL_FREQ3);writel(((1<<8) | MAIN_MDIV3), MAINPLL_DIV3);writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),MAINPLL_FREQ4);writel(((1<<8) | MAIN_MDIV4), MAINPLL_DIV4);writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),MAINPLL_FREQ5);writel(((1<<8) | MAIN_MDIV5), MAINPLL_DIV5);writel((1<<8 | MAIN_MDIV6), MAINPLL_DIV6);writel((1<<8 | MAIN_MDIV7), MAINPLL_DIV7);while ((readl(MAINPLL_CTRL) & 0x80) != 0x80);main_pll_ctrl = readl(MAINPLL_CTRL);main_pll_ctrl &= 0xFFFFFFFB;writel(main_pll_ctrl, MAINPLL_CTRL);+}
+static void ddr_pll_init_ti816x(u32 sil_index, u32 clk_index) +{
u32 ddr_pll_ctrl = 0;/** Sequence to be followed:* 1. Put the PLL in bypass mode by setting BIT2 in its ctrl reg* 2. Write the values of N,P in the CTRL reg* 3. Program the freq values, divider values for the requiredoutput
* in the Control module reg* 4. Note: Loading the freq value requires a particular bit to beset
* in the freq reg.* 5. Program the CM divider value in the CM module reg* 6. Enable the PLL by setting the appropriate bit in the CTRLreg of
* the PLL*//* If the registers have been set by the ROM code dont do anything*/
ddr_pll_ctrl = readl(DDRPLL_CTRL);ddr_pll_ctrl &= 0xFFFFFFFB;writel(ddr_pll_ctrl, DDRPLL_CTRL);ddr_pll_ctrl = readl(DDRPLL_CTRL);ddr_pll_ctrl &= 0xFFFFFFF7;ddr_pll_ctrl |= 8;writel(ddr_pll_ctrl, DDRPLL_CTRL);ddr_pll_ctrl = readl(DDRPLL_CTRL);ddr_pll_ctrl &= 0xFF;ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);writel(ddr_pll_ctrl, DDRPLL_CTRL);/* 10usec delay */ddr_delay(10);writel(0x0, DDRPLL_PWD);writel(((0<<8) | DDR_MDIV1), DDRPLL_DIV1);ddr_delay(1);writel(((1<<8) | DDR_MDIV1), DDRPLL_DIV1);writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),DDRPLL_FREQ2);writel(((1<<8) | DDR_MDIV2), DDRPLL_DIV2);writel(((0<<8) | DDR_MDIV3), DDRPLL_DIV3);ddr_delay(1);writel(((1<<8) | DDR_MDIV3), DDRPLL_DIV3);ddr_delay(1);writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),DDRPLL_FREQ3);ddr_delay(1);writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),DDRPLL_FREQ3);ddr_delay(5);/* Wait for PLL to lock */while ((readl(DDRPLL_CTRL) & 0x80) != 0x80);ddr_pll_ctrl = readl(DDRPLL_CTRL);ddr_pll_ctrl &= 0xFFFFFFFB;ddr_pll_ctrl |= 4;writel(ddr_pll_ctrl, DDRPLL_CTRL);writel(0x1, DDR_RCD);+}
+/*****************************************************************
- Routine: peripheral_enable
- Description: Enable the clks & power for perifs (TIMER1, UART0,...)
- ******************************************************************/
+static void peripheral_enable(void) +{
/* DMTimers */writel(0x2, CM_ALWON_L3_SLOW_CLKSTCTRL);/** Note on Timers:* There are 8 timers(0-7) out of which timer 0 is a secure timer.* Timer 0 mux should not be changed* For other timers, there are 3 inputs TCLKIN, 32KHz (external clk* or SYSCLK18?) and CLKIN(27MHz)* We select CLKIN and use that*//** First we need to enable the modules and setup the clk path* Then the timers need to be configured by writing to theirregisters
* To access the timer registers we need the module to be* enabled which is what we do in the first step*//* TIMER 1 */writel(0x2, CM_ALWON_TIMER_1_CLKCTRL);/* Selects CLKIN (27MHz) */writel(0x2, CM_TIMER1_CLKSEL);while (((readl(CM_ALWON_L3_SLOW_CLKSTCTRL)& (0x80000<<1)) >> (19+1)) != 1);while (((readl(CM_ALWON_TIMER_1_CLKCTRL) & 0x30000)>>16) != 0);writel(0x2, (DM_TIMER1_BASE + 0x54));while (readl(DM_TIMER1_BASE + 0x10) & 1);writel(0x1, (DM_TIMER1_BASE + 0x38));/* UARTs *//* Note: The clock has been set to correct rate before this step */writel(0x2, CM_ALWON_UART_0_CLKCTRL);while (readl(CM_ALWON_UART_0_CLKCTRL) != 0x2);writel(0x2, CM_ALWON_UART_1_CLKCTRL);while (readl(CM_ALWON_UART_1_CLKCTRL) != 0x2);writel(0x2, CM_ALWON_UART_2_CLKCTRL);while (readl(CM_ALWON_UART_2_CLKCTRL) != 0x2);while ((readl(CM_ALWON_L3_SLOW_CLKSTCTRL) & 0x2100) != 0x2100);/* eFuse */writel(0x2, CM_ALWON_CUST_EFUSE_CLKCTRL);while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != 0x2);/* GPIO0 */writel(0x2, CM_ALWON_GPIO_0_CLKCTRL);while (readl(CM_ALWON_GPIO_0_CLKCTRL) != 0x2);writel((BIT(8)), CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK);/* SPI */writel(0x2, CM_ALWON_SPI_CLKCTRL);while (readl(CM_ALWON_SPI_CLKCTRL) != 0x2);/* I2C0 */writel(0x2, CM_ALWON_I2C_0_CLKCTRL);while (readl(CM_ALWON_I2C_0_CLKCTRL) != 0x2);/* Ethernet */writel(0x2, CM_ETHERNET_CLKSTCTRL);writel(0x2, CM_ALWON_ETHERNET_0_CLKCTRL);writel(0x2, CM_ALWON_ETHERNET_1_CLKCTRL);/* HSMMC */writel(0x2, CM_ALWON_HSMMC_CLKCTRL);while (readl(CM_ALWON_HSMMC_CLKCTRL) != 0x2);/* WDT *//** For WDT to be functional, it needs to be first stopped bywriting
* the pattern 0xAAAA followed by 0x5555 in the WDT start/stopregister.
* After that a write-once register in Control module needs to* be configured* to unfreeze the timer.* Note: It is important to stop the watchdog before unfreezing it*/writel(0xAAAA, WDT_WSPR);while (readl(WDT_WWPS) != 0x0);writel(0x5555, WDT_WSPR);while (readl(WDT_WWPS) != 0x0);/* Unfreeze WDT */writel(0x2, WDT_UNFREEZE);+}
+/******************************************************************************
- prcm_init() - inits clocks for PRCM as defined in clocks.h
*****************************************************************************/ +void prcm_init(void) +{
/* For future */u32 clk_index = 0, sil_index = 0;writel(0x2, 0x48200010);
define a register name please
/* Enable the control module */writel(0x2, CM_ALWON_CONTROL_CLKCTRL);/* Fix ROM code bug */writel(0x0, 0x48180324);
what bug? define a register name
main_pll_init_ti816x(clk_index, sil_index);ddr_pll_init_ti816x(clk_index, sil_index);/** With clk freqs setup to desired values,* enable the required peripherals*/peripheral_enable();+} +#endif /* CONFIG_SPL_BUILD */
+/**********************************************************
- Routine: s_init
- Description: Does early system init of muxing and clocks.
- Called at time when only stack is available.
- **********************************************************/
+void s_init(void) +{ +#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */prcm_init();configure_module_pin_mux(mmc_pin_mux);gd = &gdata;preloader_console_init();config_ti816x_sdram_ddr(); /* Do DDR settings */+#endif +}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{
omap_mmc_init(0, 0, 0);return 0;+} +#endif diff --git a/boards.cfg b/boards.cfg index c98495a..aab56b9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -239,6 +239,7 @@ am335x_evm_uart3 arm armv7 am335x ti am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5 am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 ti814x_evm arm armv7 ti814x ti am33xx +ti816x_evm arm armv7 ti816x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 highbank arm armv7 highbank
highbankmx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h new file mode 100644 index 0000000..8d10b1c --- /dev/null +++ b/include/configs/ti816x_evm.h @@ -0,0 +1,177 @@ +/*
- ti816x_evm.h
- Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- Antoine Tenart, atenart@adeneo-embedded.com
- This file is released under the terms of GPL v2 and any later version.
- See the file COPYING in the root directory of the source tree for
details.
- */
+#ifndef __CONFIG_TI816X_EVM_H +#define __CONFIG_TI816X_EVM_H
+#define CONFIG_TI81XX +#define CONFIG_TI816X +#define CONFIG_SYS_NO_FLASH
+#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h>
+#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) +#define CONFIG_SYS_LONGHELP /* undef save memory */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "u-boot/ti816x# " +#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
+
+#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG /* required for ramdisk support */
+#include <config_cmd_default.h> /* u-boot default commands */
+#define CONFIG_VERSION_VARIABLE +#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */ +#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=yes\0"+#define CONFIG_BOOTCOMMAND \
"mmc rescan 0;" \"fatload mmc 0 0x81000000 uImage;" \"bootm 0x81000000"+#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
+/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1)
+#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
+/*
- Memtest works on 8 MB in DRAM after skipping 32MB
- from start addr of ram disk
- */
+#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64*1024*1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ (8*1024*1024))+#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */
+#define CONFIG_CMD_ASKEN +#define CONFIG_CMD_ECHO +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2
+#define CONFIG_FS_FAT
+/* Only one of the following two options (DDR3/DDR2) should be enabled */ +/* +#define CONFIG_TI816X_EVM_DDR2 +#define CONFIG_TI816X_TWO_EMIF 1 +*/ +#define CONFIG_TI816X_EVM_DDR3
+#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ +#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
+#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)+/**
- Platform/Board specific defs
- */
+#define CONFIG_SYS_CLK_FREQ 27000000 +#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#undef CONFIG_NAND_OMAP_GPMC
+/*
- NS16550 Configuration
- */
+#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
+#define CONFIG_BAUDRATE 115200
+/* allow overwriting serial config and ethaddr */ +#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SERIAL1 +#define CONFIG_SERIAL2 +#define CONFIG_SERIAL3 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_ENV_IS_NOWHERE
+/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+/* Since SPL did pll and ddr initialization for us,
- we don't need to do it twice.
- */
+#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif
+/* Unsupported features */ +#undef CONFIG_USE_IRQ
+#endif
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