Detlev,
Thanks for havnig a look at this
On Thu, Oct 29, 2009 at 3:13 AM, Detlev Zundel dzu@denx.de wrote:
Hello Graeme,
This patch does two things:
- Changes default behaviour to use proper memory accessors
- Allows port-mapped access (using inb/outb) for the x86 architecture
Signed-off-by: Graeme Russ graeme.russ@gmail.com
drivers/serial/ns16550.c | 69 ++++++++++++++++++++++++++-------------------- 1 files changed, 39 insertions(+), 30 deletions(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 2fcc8c3..c41ca0d 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -6,6 +6,8 @@
#include <config.h> #include <ns16550.h> +#include <linux/types.h> +#include <asm/io.h>
#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ @@ -13,28 +15,35 @@ #define UART_FCRVAL (UART_FCR_FIFO_EN | \ UART_FCR_RXSR | \ UART_FCR_TXSR) /* Clear & enable FIFOs */ +#ifdef CONFIG_X86 +#define uart_writeb(x,y) outb(x,(ulong)y) +#define uart_readb(y) inb((ulong)y) +#else +#define uart_writeb(x,y) writeb(x,y) +#define uart_readb(y) readb(y) +#endif
Why do you need a specific variant for X86 instead of implementing writeb and readb correctly in the first place?
For x86 readb and writeb provide volatile accessors to memory - These are used for memory-mapped devices (i.e. devices which are attached directly to the memory bus such as PCI devices etc). inb and outb provide access to I/O Ports. For example:
writeb(0x12, 0x00001000) will generate something like: movb $0x12, al movl $0x00001000, ebx movb al, ebx
outb(0x12, 0x00001000) will generate something like: movb $0x12, al movl $0x00001000, ebx outb al, ebx
Looking at include/asm/asm-ppc/io.h it seems to me that, for PPC, there is no differentiation between readb/writeb and inb/outb other than that the user may define an optional IOBASE for inb/outb which shifts where in memory inb/outb accesses, but they are still memory accesses. So, for PPC, if IOBASE is 0, the above two examples will compile to identical code.
(Having a look at the other arches, it appears that x86 is very unique in that inb/outb do not access memory)
If this was in place, all the accessors should only switch to using readb/writeb and from looking at it, this should not brak e.g. PowerPC boards with weird register layouts.
This patch should not change the behaviour for non x86 boards other than to use proper I/O accessors which prevents any risk that gcc will optimise them into some other order (or completely out)
For x86, this patch causes the driver to use I/O rather than memory which is how PC UARTS (and interrupt controllers and nearly anything else which is not 'memory') have always been accessed
When you post a patch with only these changes, I'll test it on a few of the usual suspects on PowerPC.
The only other option is my even uglier first patch:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/70250
Cheers Detlev
Regards,
Graeme