On 13/12/2011 14:44, Jason Liu wrote:
This enable the network function on the i.mx6q armadillo2 board(arm2), thus we can use tftp to load image from network.
Cc: Stefano Babic sbabic@denx.de Signed-off-by: Jason Liu jason.hui@linaro.org Tested-by: Dirk Behme dirk.behme@de.bosch.com
board/freescale/mx6qarm2/mx6qarm2.c | 90 +++++++++++++++++++++++++++++++++++ include/configs/mx6qarm2.h | 13 ++++- 2 files changed, 101 insertions(+), 2 deletions(-)
Hi Jason,
only a couple of minor issues.
#ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR, 1}, @@ -132,9 +162,69 @@ int board_mmc_init(bd_t *bis) } #endif
+#define MII_MMD_ACCESS_CTRL_REG 0xd +#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe +#define MII_DBG_PORT_REG 0x1d +#define MII_DBG_PORT2_REG 0x1e
+int fecmxc_mii_postcall(int phy) +{
- unsigned short val;
- /*
* Due to the i.MX6Q Armadillo2 board HW design,there is* no 125Mhz clock input from SOC. In order to use RGMII,* We need enable AR8031 ouput a 125MHz clk from CLK_25M*/- miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
- miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
- miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
- miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
- val &= 0xffe3;
- val |= 0x18;
- miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
- /* For the RGMII phy, we need enable tx clock delay */
- miiphy_write("FEC", phy, 0x1d, 0x5);
You define MII_DBG_PORT_REG, but then you do not use it.
- miiphy_read("FEC", phy, 0x1e, &val);
The same here for MII_DBG_PORT2_REG. Can you also defines some constants for the value you are setting (tx clock delay, etc.).
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index a7b363d..3a30679 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -56,6 +56,17 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC"
I have not thought this is needed. I see only one controller.
Best regards, Stefano Babic