Dear York Sun,
In message 1363973052-25918-17-git-send-email-yorksun@freescale.com you wrote:
From: Liu Gang Gang.Liu@freescale.com
Add the tlb entries based on the configuration of the SRIO interfaces. Every SRIO interface has 256M space:
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
Signed-off-by: Liu Gang Gang.Liu@freescale.com
board/freescale/b4860qds/tlb.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)
CHECK: Alignment should match open parenthesis #147: FILE: board/freescale/b4860qds/tlb.c:131: + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
CHECK: Alignment should match open parenthesis #153: FILE: board/freescale/b4860qds/tlb.c:137: + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
Best regards,
Wolfgang Denk