The command miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr) always returns 8 for the PHY address. It is the reset value for the PHY Address Register. Obviously, this default value could be incorrect. Moreover, as the PHY address is well known, there is no need to auto-detect it.
Now, the PHY address must given as a parameter to the PHY initialization function. Additionally this patch also fixes some aesthetic issues.
Signed-off-by: Simon Guinot simon.guinot@sequanux.org --- board/LaCie/common/common.c | 23 +++++++---------------- board/LaCie/common/common.h | 2 +- board/LaCie/edminiv2/edminiv2.c | 2 +- board/LaCie/net2big_v2/net2big_v2.c | 2 +- board/LaCie/netspace_v2/netspace_v2.c | 2 +- 5 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index dc5350d..78d0edc 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -20,34 +20,25 @@ #define MV88E1116_RGMII_TXTM_CTRL (1 << 4) #define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-void mv_phy_88e1116_init(const char *name) +void mv_phy_88e1116_init(const char *name, u16 phyaddr) { u16 reg; - u16 devadr;
if (miiphy_set_current_dev(name)) return;
- /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..(%s) could not read PHY dev address\n", __func__); - return; - } - /* * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 4.7.2 of chip datasheet */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
- printf("88E1116 Initialized on %s\n", name); + if (miiphy_reset(name, phyaddr) == 0) + printf("88E1116 Initialized on %s\n", name); } #endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h index 82a9522..2edd5ab 100644 --- a/board/LaCie/common/common.h +++ b/board/LaCie/common/common.h @@ -11,7 +11,7 @@ #define _LACIE_COMMON_H
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -void mv_phy_88e1116_init(const char *name); +void mv_phy_88e1116_init(const char *name, u16 phyaddr); #endif #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) int lacie_read_mac_address(uchar *mac); diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 1b33875..4a9b308 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -96,6 +96,6 @@ int board_init(void) /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif /* CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index d0b4adf..d931d1e 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -109,7 +109,7 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif
diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index fbf020f..3f255ef 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -107,7 +107,7 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif