
28 Aug
2015
28 Aug
'15
11:03 p.m.
On Mon, Aug 17, 2015 at 07:58:34PM +0530, Lokesh Vutla wrote:
ARM supported speeds and init value of core_pll for SDP1200 are programmed wrong as part for the device speed cleanups. Fixing it here. Thanks to "Vitaly Andrianov vitalya@ti.com" for bisecting this issue
Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection") Tested-by: Vitaly Andrianov vitalya@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Applied to u-boot/master, thanks!
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Tom