On Wed, Jul 17, 2019 at 9:31 AM Jagan Teki jagan@amarulasolutions.com wrote:
On Wed, Jul 17, 2019 at 9:20 AM Anup Patel Anup.Patel@wdc.com wrote:
From: Bhargav Shah bhargavshah1988@gmail.com
This patch adds SiFive SPI driver. The driver is 100% DM driver and it determines input clock using clk framework.
The SiFive SPI block is found on SiFive FU540 SOC and is used to access flash and MMC devices on SiFive Unleashed board.
This driver implementation is inspired from the Linux SiFive SPI driver available in Linux-5.2 or higher and SiFive FSBL sources.
Signed-off-by: Bhargav Shah bhargavshah1988@gmail.com Signed-off-by: Anup Patel anup.patel@wdc.com Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com
drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-sifive.c | 375 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 384 insertions(+) create mode 100644 drivers/spi/spi-sifive.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index eb32f082fe..030f3377d4 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -224,6 +224,14 @@ config SANDBOX_SPI }; };
+config SPI_SIFIVE
bool "SiFive SPI driver"helpThis driver supports the SiFive SPI IP. If unsure say N.Enable the SiFive SPI controller driver.The SiFive SPI controller driver is found on various SiFive SoCs.config SPI_SUNXI bool "Allwinner SoC SPI controllers" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8be9a4baa2..a53b9f4217 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o +obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c new file mode 100644 index 0000000000..08f30f3f21 --- /dev/null +++ b/drivers/spi/spi-sifive.c @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2018 SiFive, Inc.
- Copyright 2019 Bhargav Shah bhargavshah1988@gmail.com
- SiFive SPI controller driver (master mode only)
- */
+#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <linux/log2.h> +#include <clk.h>
+#define SIFIVE_SPI_MAX_CS 32
+#define SIFIVE_SPI_DEFAULT_DEPTH 8 +#define SIFIVE_SPI_DEFAULT_BITS 8
+/* register offsets */ +#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */ +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ +#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */ +#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */ +#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */ +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ +#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */ +#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */ +#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */ +#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */ +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */ +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */ +#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */ +#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
+/* sckdiv bits */ +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
+/* sckmode bits */ +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) +#define SIFIVE_SPI_SCKMODE_POL BIT(1) +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
SIFIVE_SPI_SCKMODE_POL)+/* csmode bits */ +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
+/* delay0 bits */ +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
+/* delay1 bits */ +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU +#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
+/* fmt bits */ +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U +#define SIFIVE_SPI_FMT_PROTO_DUAL 1U +#define SIFIVE_SPI_FMT_PROTO_QUAD 2U +#define SIFIVE_SPI_FMT_PROTO_MASK 3U +#define SIFIVE_SPI_FMT_ENDIAN BIT(2) +#define SIFIVE_SPI_FMT_DIR BIT(3) +#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16) +#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
+/* txdata bits */ +#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU +#define SIFIVE_SPI_TXDATA_FULL BIT(31)
+/* rxdata bits */ +#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU +#define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
+/* ie and ip bits */ +#define SIFIVE_SPI_IP_TXWM BIT(0) +#define SIFIVE_SPI_IP_RXWM BIT(1)
+struct sifive_spi {
void *regs; /* base address of the registers */u32 fifo_depth;u32 bits_per_word;u32 cs_inactive; /* Level of the CS pins when inactive*/u32 freq;u32 num_cs;+};
+static void sifive_spi_prep_device(struct sifive_spi *spi,
struct dm_spi_slave_platdata *slave)+{
/* Update the chip select polarity */if (slave->mode & SPI_CS_HIGH)spi->cs_inactive &= ~BIT(slave->cs);elsespi->cs_inactive |= BIT(slave->cs);writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);/* Select the correct device */writel(slave->cs, spi->regs + SIFIVE_SPI_REG_CSID);+}
+static int sifive_spi_set_cs(struct sifive_spi *spi,
struct dm_spi_slave_platdata *slave)+{
u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;if (slave->cs > spi->num_cs)return -EINVAL;Move this to cs_info.
Sure, will do.
if (slave->mode & SPI_CS_HIGH)cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);return 0;+}
+static void sifive_spi_clear_cs(struct sifive_spi *spi) +{
writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE);+}
+static void sifive_spi_prep_transfer(struct sifive_spi *spi,
bool is_rx_xfer,struct dm_spi_slave_platdata *slave)+{
u32 cr;/* Modify the SPI protocol mode */cr = readl(spi->regs + SIFIVE_SPI_REG_FMT);/* Bits per word ? */cr &= ~SIFIVE_SPI_FMT_LEN_MASK;cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);/* LSB first? */cr &= ~SIFIVE_SPI_FMT_ENDIAN;if (slave->mode & SPI_LSB_FIRST)cr |= SIFIVE_SPI_FMT_ENDIAN;/* Number of wires ? */cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD))cr |= SIFIVE_SPI_FMT_PROTO_QUAD;else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL))cr |= SIFIVE_SPI_FMT_PROTO_DUAL;elsecr |= SIFIVE_SPI_FMT_PROTO_SINGLE;/* SPI direction in/out ? */cr &= ~SIFIVE_SPI_FMT_DIR;if (!is_rx_xfer)cr |= SIFIVE_SPI_FMT_DIR;writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);+}
+static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr) +{
u32 data;do {data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA);} while (data & SIFIVE_SPI_RXDATA_EMPTY);if (rx_ptr)*rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;+}
+static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr) +{
u32 data;u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :SIFIVE_SPI_TXDATA_DATA_MASK;do {data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA);} while (data & SIFIVE_SPI_TXDATA_FULL);writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);+}
+static int sifive_spi_claim_bus(struct udevice *dev) +{
/* Nothing to do here. */return 0;+}
+static int sifive_spi_release_bus(struct udevice *dev) +{
/* Nothing to do here. */return 0;+}
dummy won't need as spi-uclass.c return 0 if none hooked.
Okay, I will update.
Regards, Anup