To avoid the duplicated code, add the PLLB handle functions.
Signed-off-by: Wenyou Yang wenyou.yang@atmel.com Reviewed-by: Andreas Bießmann andreas.devel@googlemail.com ---
Changes in v2: None
arch/arm/mach-at91/arm926ejs/clock.c | 38 +++++++++++++++++++++++++++++++++ arch/arm/mach-at91/include/mach/clk.h | 2 ++ 2 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index c8b5e10..c8d24ae 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -18,6 +18,8 @@ # error You need to define CONFIG_AT91FAMILY in your board config! #endif
+#define EN_PLLB_TIMEOUT 500 + DECLARE_GLOBAL_DATA_PTR;
static unsigned long at91_css_to_rate(unsigned long css) @@ -242,3 +244,39 @@ void at91_mck_init(u32 mckr) while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) ; } + +int at91_pllb_clk_enable(u32 pllbr) +{ + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + start_time = get_timer(0); + writel(pllbr, &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) { + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) { + printf("ERROR: failed to enable PLLB\n"); + return -1; + } + } + + return 0; +} + +int at91_pllb_clk_disable(void) +{ + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + start_time = get_timer(0); + writel(0, &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) { + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) { + printf("ERROR: failed to disable PLLB\n"); + return -1; + } + } + + return 0; +} diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h index b2604ef..64dec52 100644 --- a/arch/arm/mach-at91/include/mach/clk.h +++ b/arch/arm/mach-at91/include/mach/clk.h @@ -133,5 +133,7 @@ void at91_system_clk_disable(int sys_clk); int at91_upll_clk_enable(void); int at91_upll_clk_disable(void); void at91_usb_clk_init(u32 value); +int at91_pllb_clk_enable(u32 pllbr); +int at91_pllb_clk_disable(void);
#endif /* __ASM_ARM_ARCH_CLK_H__ */