Rahanesh said the following on 03/04/2009 01:23 PM:
I am trying to set up vector table for a my custom RTOS.
ARM provides 0x0000:0000 and 0xFFFF:0000 as the Vector base address.
I planned to use 0x0000:0000 for my development.
I have decided to hard-code the opcode for the corresponding branches to the loactions respectively.(0x00000000 to 0x0000001C)
When i write to 0x00000000 location , i get a prefetch abort exception. Why am i not able to write to 0x00000000?
Some basics on interrupt vector handling on cortex_a8: CP15 coprocessor forallows: * legacy high and low interrupt vectors * also allows you to program interrupt vector of your choosing. please read the ARM architecture Manual and the ARM technical reference manual for further information. if you look at the OMAP3 TRM, you will find 0x0 belonging to GPMC address space, unless you mapped something there, ARM will not find an vector to execute.
How did U boot handle this? How did U boot set up Vector table?
in OMAP3, we have rom code which setups a trampoline vector in SRAM. this is piggybacked to handle the interrupts. the omap3 code probably does not use interrupts extensively at this stage, but yeah, that is one way to do it.. but you would need ROM Code executing prior to your code to get this.
one way to go about this is to enable MMU and map 0x0 to which ever address space you want (if you want to use the "old style" of doing arm interrupts..
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Regards, Nishanth Menon