On Mon, 22 Dec 2014 17:35:02 +0800 Chen-Yu Tsai wens@csie.org wrote:
Hi Hans,
On Sat, Dec 20, 2014 at 7:29 PM, Hans de Goede hdegoede@redhat.com wrote:
Hi Ian, et al,
Here is a v2 of the A23 patches which did not pass review in v1 (so not a resend of the whole set).
I just built a new u-boot for my Q8H tablet this morning against
289dcd4 sunxi: video: Set input sync enable
and it works nicely. One thing that's not correct, but isn't an immediate issue is that PLL1 is different between sun6i and sun8i. See:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/diff/drivers/clk/sunxi/clk-sunxi.c?id=515c1a4This results in the CPU clock speed being only 504 MHz instead of the configured 1008 MHz full speed. As I said, it's not an immediate issue. In the future with cpufreq, it shouldn't matter either.
Thanks, that's a good catch. Do you happen to know if PLL5 is the same or different between sun6i and sun8i?
The circumstances around the "sun6i: Add k and m parameters to clock_set_pll5()" patch seem to be a little bit fishy to me: http://lists.denx.de/pipermail/u-boot/2014-December/199279.html