Hi York,
On 16 March 2017 at 16:47, Simon Glass sjg@chromium.org wrote:
On 9 February 2017 at 11:35, York Sun york.sun@nxp.com wrote:
When adding local memory to PCI region, gd->ram_size is correct only if the memory is in one continuous block. In case memory is split into several banks, each bank should be added separately.
Signed-off-by: York Sun york.sun@nxp.com CC: Simon Glass sjg@chromium.org
It was spotted when I was rewriting the code to reserve secure memory and forgot to reduce gd->ram_size. PCIe resumes working after fixing gd->ram_size. For my case, the memory is split into two banks. So base + gd->ram_size is not in memory. I don't know how it worked before. This change seems reasonable without digging into PCI code.
drivers/pci/pci-uclass.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
Acked-by: Simon Glass sjg@chromium.org
Unfortunately this breaks chromebook_link (x86).
Do you have any ideas or should I dig into it?
Regards, Simon