On Mar 22, 2010, at 5:51 PM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message 1269194951-17996-1-git-send-email-galak@kernel.crashing.org you wrote:
From: Dave Liu daveliu@freescale.com
Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance.
Signed-off-by: Dave Liu daveliu@freescale.com
cpu/mpc8xxx/ddr/ctrl_regs.c | 19 +++++++++++++------ 1 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index adc4f6e..caac943 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,5 +1,5 @@ /*
- Copyright 2008-2009 Freescale Semiconductor, Inc.
- Copyright 2008-2010 Freescale Semiconductor, Inc.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
...
- Version 2 as published by the Free Software Foundation.
As it turns out, basicly all FSL DDR code (and lots more of the FSL code) are GPL v2 only:
board/freescale/mpc8323erdb/mpc8323erdb.c board/freescale/mpc8536ds/ddr.c board/freescale/mpc8540ads/ddr.c board/freescale/mpc8541cds/ddr.c board/freescale/mpc8544ds/ddr.c board/freescale/mpc8548cds/ddr.c board/freescale/mpc8555cds/ddr.c board/freescale/mpc8560ads/ddr.c board/freescale/mpc8568mds/ddr.c board/freescale/mpc8572ds/ddr.c board/freescale/mpc8610hpcd/ddr.c board/freescale/mpc8641hpcn/ddr.c board/freescale/mpc8569mds/ddr.c board/freescale/p2020ds/ddr.c board/mpc8540eval/ddr.c cpu/mpc85xx/ddr-gen2.c cpu/mpc85xx/ddr-gen1.c cpu/mpc85xx/ddr-gen3.c cpu/mpc86xx/ddr-8641.c cpu/mpc86xx/fdt.c cpu/mpc8xxx/ddr/common_timing_params.h cpu/mpc8xxx/ddr/Makefile cpu/mpc8xxx/ddr/lc_common_dimm_params.c cpu/mpc8xxx/ddr/ddr.h cpu/mpc8xxx/ddr/ddr1_dimm_params.c cpu/mpc8xxx/ddr/ddr2_dimm_params.c cpu/mpc8xxx/ddr/main.c cpu/mpc8xxx/ddr/ddr3_dimm_params.c cpu/mpc8xxx/ddr/util.c cpu/mpc8xxx/ddr/ctrl_regs.c cpu/mpc8xxx/ddr/options.c cpu/mpc8xxx/Makefile drivers/i2c/fsl_i2c.c drivers/pci/fsl_pci_init.c include/asm-m68k/fsl_i2c.h include/asm-ppc/fsl_i2c.h include/asm-ppc/fsl_ddr_dimm_params.h include/asm-ppc/fsl_law.h include/asm-ppc/mpc8xxx_spi.h include/asm-ppc/fsl_dma.h include/asm-ppc/fsl_ddr_sdram.h include/configs/MPC8323ERDB.h include/configs/MPC8610HPCD.h etc. etc.
Can we please fix this?
I'm looking into it, but am not holding up these patches on it. Ok?
- k