Move U_BOOT_DRIVER() entry from the data file (clk-uniphier-mio.c) to the core support file (clk-uniphier-core.c) because I do not want to repeat the driver boilerplate when I add more clock data.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/clk/uniphier/clk-uniphier-core.c | 88 ++++++++++++++++++++++++++------ drivers/clk/uniphier/clk-uniphier-mio.c | 47 +---------------- drivers/clk/uniphier/clk-uniphier.h | 14 +---- 3 files changed, 74 insertions(+), 75 deletions(-)
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 721e59e..2db4a7c 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -14,6 +14,35 @@
#include "clk-uniphier.h"
+/** + * struct uniphier_clk_priv - private data for UniPhier clock driver + * + * @base: base address of the clock provider + * @socdata: SoC specific data + */ +struct uniphier_clk_priv { + void __iomem *base; + const struct uniphier_clk_soc_data *socdata; +}; + +int uniphier_clk_probe(struct udevice *dev) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = devm_ioremap(dev, addr, SZ_4K); + if (!priv->base) + return -ENOMEM; + + priv->socdata = (void *)dev_get_driver_data(dev); + + return 0; +} + static int uniphier_clk_enable(struct clk *clk) { struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); @@ -128,20 +157,47 @@ const struct clk_ops uniphier_clk_ops = { .set_rate = uniphier_clk_set_rate, };
-int uniphier_clk_probe(struct udevice *dev) -{ - struct uniphier_clk_priv *priv = dev_get_priv(dev); - fdt_addr_t addr; - - addr = dev_get_addr(dev); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - - priv->base = devm_ioremap(dev, addr, SZ_4K); - if (!priv->base) - return -ENOMEM; - - priv->socdata = (void *)dev_get_driver_data(dev); +static const struct udevice_id uniphier_clk_match[] = { + { + .compatible = "socionext,ph1-sld3-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-ld4-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-pro4-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-sld8-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-pro5-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,proxstream2-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-ld11-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-ld20-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { /* sentinel */ } +};
- return 0; -} +U_BOOT_DRIVER(uniphier_clk) = { + .name = "uniphier-clk", + .id = UCLASS_CLK, + .of_match = uniphier_clk_match, + .probe = uniphier_clk_probe, + .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv), + .ops = &uniphier_clk_ops, +}; diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c index 40c1b78..c1e7197 100644 --- a/drivers/clk/uniphier/clk-uniphier-mio.c +++ b/drivers/clk/uniphier/clk-uniphier-mio.c @@ -132,54 +132,9 @@ static const struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = { UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */ };
-static const struct uniphier_clk_soc_data uniphier_mio_clk_data = { +const struct uniphier_clk_soc_data uniphier_mio_clk_data = { .gate = uniphier_mio_clk_gate, .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate), .rate = uniphier_mio_clk_rate, .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate), }; - -static const struct udevice_id uniphier_mio_clk_match[] = { - { - .compatible = "socionext,ph1-sld3-mioctrl", - .data = (ulong)&uniphier_mio_clk_data, - }, - { - .compatible = "socionext,ph1-ld4-mioctrl", - .data = (ulong)&uniphier_mio_clk_data, - }, - { - .compatible = "socionext,ph1-pro4-mioctrl", - .data = (ulong)&uniphier_mio_clk_data, - }, - { - .compatible = "socionext,ph1-sld8-mioctrl", - .data = (ulong)&uniphier_mio_clk_data, - }, - { - .compatible = "socionext,ph1-pro5-mioctrl", - .data = (ulong)&uniphier_mio_clk_data, - }, - { - .compatible = "socionext,proxstream2-mioctrl", - .data = (ulong)&uniphier_mio_clk_data, - }, - { - .compatible = "socionext,ph1-ld11-mioctrl", - .data = (ulong)&uniphier_mio_clk_data, - }, - { - .compatible = "socionext,ph1-ld20-mioctrl", - .data = (ulong)&uniphier_mio_clk_data, - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(uniphier_mio_clk) = { - .name = "uniphier-mio-clk", - .id = UCLASS_CLK, - .of_match = uniphier_mio_clk_match, - .probe = uniphier_clk_probe, - .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv), - .ops = &uniphier_clk_ops, -}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 4e9f7dc..0b60337 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -40,18 +40,6 @@ struct uniphier_clk_soc_data { .rate = f, \ }
-/** - * struct uniphier_clk_priv - private data for UniPhier clock driver - * - * @base: base address of the clock provider - * @socdata: SoC specific data - */ -struct uniphier_clk_priv { - void __iomem *base; - const struct uniphier_clk_soc_data *socdata; -}; - -extern const struct clk_ops uniphier_clk_ops; -int uniphier_clk_probe(struct udevice *dev); +extern const struct uniphier_clk_soc_data uniphier_mio_clk_data;
#endif /* __CLK_UNIPHIER_H__ */