Not every version and revision of the Cortex-A8 ARM core requires the same errata workarounds. In addition, enabling those requires to have similar workarounds enabled in the kernel or it will cause numerous segmentation faults.
This enables those workarounds when they are needed, according to what is done in Linux.
Follow-up to the discussion from July 2013: http://lists.denx.de/pipermail/u-boot/2013-July/158377.html --- arch/arm/cpu/armv7/omap3/board.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 90d6ae7..a87dd2a 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -431,14 +431,29 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
static void omap3_setup_aux_cr(void) { - /* Workaround for Cortex-A8 errata: #454179 #430973 - * Set "IBE" bit - * Set "Disable Branch Size Mispredicts" bit - * Workaround for erratum #621766 + u32 id, revision, variant; + u32 bits = 0; + + asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (id)); + + variant = (id & 0xf00000) >> 20; + revision = id & 0x0f; + + /* Workaround for Cortex-A8 erratum: #454179 #430973 + * Set IBE bit + * Set Disable Branch Size Mispredicts (DBSM) bit + */ + if (variant < 2) + bits |= (1 << 6) | (1 << 7); + + /* Workaround for Cortex-A8 erratum #621766 * Enable L1NEON bit - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 */ - omap3_update_aux_cr_secure(0xE0, 0); + if (variant == 2 && revision == 0) + bits |= (1 << 5); + + if (bits != 0) + omap3_update_aux_cr_secure(bits, 0); }
#ifndef CONFIG_SYS_L2CACHE_OFF