
On Thu, Apr 24, 2008 at 08:53:53AM -0700, David Hawkins wrote:
Given that you don't think any of my suggestions are possible, I'll have to go download the ppc460 reference manual and convince myself :)
Ame, feel free to chime in if you think any of the ideas are possible.
So maybe I need to clarify some more. The PPC460 data sheet is not too clear on this yet. However, here are my thoughts on this. Lets just take the simple case as an example. We have a plurality of 460s where a single one is the master. Between the master and all the slaves is a PCI bridge. The slaves are hardwired to boot from pci bus memory -- according to the datasheet that is at a fixed address. So there does not appear to be any need to do anything to the slave upon power up. Now the master boots and then allocates a chunk of contiguous memory using a kernel driver or whatever is needed. The image is just whatever the flash image would normally contain (uboot + kernel + rootfs). The address of that chunk is then given to the pci bridge so that it can perform inbound translation from the address that the PPC slaves will use to the address where the image is physically located. Then the slaves are taken out of reset and begin reading "flash" across the pci bus which really goes through the bridge and is mapped to the DRAM on the master (or I guess it could be the flash on the master, but DRAM seemed easier since it is already running).
Ok, so how many holes does this approach have?
Thanks - ame