On 2/26/20 6:59 PM, Fabio Estevam wrote:
Hi Giulio,
On Wed, Feb 26, 2020 at 2:54 PM Giulio Benetti giulio.benetti@benettiengineering.com wrote:
Yes, it's a good idea. Doing this I've taken this[1] as example. So I don't know where in u-boot PLLs are initialized according to a dts file, can you please provide me an example? I will be happy to modify this according to that!
In the kernel device trees we use the 'assigned-clocks' and 'assigned-clock-parents' properties to establish a clock parent relationship.
I suggest we follow the same approach in U-Boot.
Oh, I've seen now, need to study it before, but now in my mind it's getting more clear how that works. But will this work even if shrinked CCF in u-boot can't set parent clocks(at least this is what I've understood)? I mean, basically here for LCDIF I see that only last divider get set for achieving pixel-clock, while all parents are get only to recalcute the "last divider parent clock".
Also, I can't understand, is it ok setting PLL5 to 650Mhz and un-bypass it? The problem is only about clk_set_parent() for LCDIF?
Because if a peripheral would set a PLL5 frequency and another peripheral use it as parent, then it would set it again.
Best regards