On 03/01/22 10:38AM, Tudor.Ambarus@microchip.com wrote:
Hi,
On 12/29/21 7:56 AM, JaimeLiao wrote:
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Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding Macronix flash in Octal DTR mode.
Enable Octal DTR mode with 20 dummy cycles to allow running at the maximum supported frequency. -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,...
Signed-off-by: JaimeLiao jaimeliao.tw@gmail.com
drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 12 ++++- 2 files changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index d5d905fa5a..0a6550984b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = { }; #endif /* CONFIG_SPI_FLASH_MT35XU */
+#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX) +/**
- spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
- @nor: pointer to a 'struct spi_nor'
- Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
- Bit 2 of Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
- Return: 0 on success, -errno otherwise.
- */
+static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
This method should be called just for the flashes that do not define the JESD216 "Command Sequences to Change to Octal DDR (8D-8D-8D) mode" table. Or where SFDP is skipped intentionally.
When adding Octal DTR support to kernel and U-Boot SPI NOR, I did consider parsing this table. But I dropped the idea at the time because the table guarantees to only use 20 dummy cycles for reads and operation at 100 MHz (or higher if supported). But this does not guarantee that we can run the flash at the maximum speed possible. For example, for Spansion S28 flash we can only go up to 166 MHz with 20 dummy cycles. For getting 200 MHz we need at least 23 dummy cycles.