17 Jun
2017
17 Jun
'17
3:41 p.m.
Hi Simon,
On Sat, Jun 17, 2017 at 11:44 AM, Simon Glass sjg@chromium.org wrote:
On 16 June 2017 at 07:31, Bin Meng bmeng.cn@gmail.com wrote:
GPIO bank E pin 8 & 9 are used to control the on-board two USB ports VBUS on/off. Let's configure them in the misc_init_r().
Signed-off-by: Bin Meng bmeng.cn@gmail.com
board/intel/minnowmax/minnowmax.c | 53 +++++++++++++++++++++++++++++++++++++++ include/configs/minnowmax.h | 1 + 2 files changed, 54 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
I wonder if this GPIO information could/should be in the device tree?
The GPIO pin info is currently under the pinctlr node in the device tree, but the GPIO programming codes in the pinctlr driver are not working on BayTrail due to GPIO "use-lvl-write-cache" behavior.
Regards, Bin