23 Apr
2014
23 Apr
'14
11:57 p.m.
On 03/08/2014 03:15 AM, Prabhakar Kushwaha wrote:
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs.
So Slow MDC clock to comply IEEE specs
Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com
Changes for v2: Update commit message
Applied to u-boot-mpc85xx/master, thanks.
York