[U-Boot] [RFC PATCH 2/2] USB: xHCI: Add stack support for xHCI

This adds stack layer for eXtensible Host Controller Interface which facilitates use of USB 3.0 in host mode.

This work is based on xHCI host controller driver in linux-kernel by Sarah Sharp. The code corresponding to xhci.c, xhci-mem.c, xhci-ring.c and xhci-hub.c in linux-kernel is grouped together here in single driver 'xhci.c'.

Signed-off-by: Vikas C Sajjan vikas.sajjan@samsung.com Signed-off-by: Vivek Gautam gautam.vivek@samsung.com --- drivers/usb/host/xhci.c | 3330 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/xhci.h | 1360 +++++++++++++++++++ 2 files changed, 4690 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/xhci.c create mode 100644 drivers/usb/host/xhci.h

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c new file mode 100644 index 0000000..bebb760 --- /dev/null +++ b/drivers/usb/host/xhci.c @@ -0,0 +1,3330 @@ +/* + * USB HOST XHCI Controller stack + * + * Copyright (C) 2012 Samsung Electronics Co.Ltd + * Vivek Gautam gautam.vivek@samsung.com + * Vikas Sajjan vikas.sajjan@samsung.com + * + * Based on xHCI host controller driver in linux-kernel + * by Sarah Sharp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/** + * This file gives the xhci stack for usb3.0 looking into + * xhci specification Rev1.0 (5/21/10). + * The quirk devices support hasn't been given yet. + */ + +#include <common.h> +#include <asm/byteorder.h> +#include <usb.h> +#include <asm/io.h> +#include <malloc.h> +#include <watchdog.h> +#include <asm/cache.h> +#include <asm-generic/errno.h> +#include "xhci.h" + +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +#define XHCI_TRB 0xC0DEABCD +#define XHCI_CTX 0xCAFEABCD + +static struct descriptor { + struct usb_hub_descriptor hub; + struct usb_device_descriptor device; + struct usb_linux_config_descriptor config; + struct usb_linux_interface_descriptor interface; + struct usb_endpoint_descriptor endpoint; + struct usb_ss_ep_comp_descriptor ep_companion; +} __attribute__ ((packed)) descriptor = { + { + 0xc, /* bDescLength */ + 0x2a, /* bDescriptorType: hub descriptor */ + 2, /* bNrPorts -- runtime modified */ + 0, /* wHubCharacteristics */ + 10, /* bPwrOn2PwrGood */ + 0, /* bHubCntrCurrent */ + {}, /* Device removable */ + {} /* at most 7 ports! XXX */ + }, + { + 0x12, /* bLength */ + 1, /* bDescriptorType: UDESC_DEVICE */ + cpu_to_le16(0x0300), /* bcdUSB: v3.0 */ + 9, /* bDeviceClass: UDCLASS_HUB */ + 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ + 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */ + 9, /* bMaxPacketSize: 512 bytes 2^9 */ + 0x0000, /* idVendor */ + 0x0000, /* idProduct */ + cpu_to_le16(0x0100), /* bcdDevice */ + 1, /* iManufacturer */ + 2, /* iProduct */ + 0, /* iSerialNumber */ + 1 /* bNumConfigurations: 1 */ + }, + { + 0x9, + 2, /* bDescriptorType: UDESC_CONFIG */ + cpu_to_le16(0x19), + 1, /* bNumInterface */ + 1, /* bConfigurationValue */ + 0, /* iConfiguration */ + 0x40, /* bmAttributes: UC_SELF_POWER */ + 0 /* bMaxPower */ + }, + { + 0x9, /* bLength */ + 4, /* bDescriptorType: UDESC_INTERFACE */ + 0, /* bInterfaceNumber */ + 0, /* bAlternateSetting */ + 1, /* bNumEndpoints */ + 9, /* bInterfaceClass: UICLASS_HUB */ + 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ + 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ + 0 /* iInterface */ + }, + { + 0x7, /* bLength */ + 5, /* bDescriptorType: UDESC_ENDPOINT */ + 0x81, /* bEndpointAddress: IN endpoint 1 */ + 3, /* bmAttributes: UE_INTERRUPT */ + 8, /* wMaxPacketSize */ + 255 /* bInterval */ + }, + { + 0x06, /* ss_bLength */ + 0x30, /* ss_bDescriptorType: SS EP Companion */ + 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */ + /* ss_bmAttributes: 1 packet per service interval */ + 0x00, + /* ss_wBytesPerInterval: 15 bits for max 15 ports */ + 0x02, + }, +}; + +struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; + +/** + * Aligns the given length to 64 bytes + * + * @param length length to be aligned + * @return aligned length + */ +unsigned int xhci_getalignedlength(unsigned int length) +{ + + unsigned int aligned_length = 0; + unsigned int remain = 0; + unsigned int toAdd = 0; + + remain = (length % 0x40); + toAdd = remain ? (0x40 - remain) : 0; + aligned_length = length + toAdd; + + return aligned_length; +} + +/** + * flushs/invalidates the address passed till the length + * + * @param addr pointer to "segement" to be freed + * @param type_len holds either the Data structure type + * OR the length of the cache line to be flushed/invalidated + * @param flush boolean to hold the flag for flushing/invalidating + * @return none + */ +void xhci_flush_inval_cache(uint32_t addr, u32 type_len, bool flush) +{ + + if ((void *)addr == NULL || flush > 1 || type_len == 0) { + debug("addr %u flush %d type_len %u\n", addr, flush, type_len); + return; + } + + /* + * "type_len" holds either the Data structure type + * OR + * the length of the cache line to be flushed/invalidated + */ + switch(type_len){ + + case XHCI_TRB: + if (flush) { + flush_dcache_range(addr, addr + + xhci_getalignedlength(sizeof(union xhci_trb))); + } else { + invalidate_dcache_range(addr, addr + + xhci_getalignedlength(sizeof(union xhci_trb))); + } + break; + case XHCI_CTX: + if (flush) { + flush_dcache_range(addr, addr + + xhci_getalignedlength(sizeof(struct xhci_container_ctx))); + } else { + invalidate_dcache_range(addr, addr + + xhci_getalignedlength(sizeof(struct xhci_container_ctx))); + } + break; + default: + if (flush) { + flush_dcache_range(addr, addr + + xhci_getalignedlength(type_len)); + } else { + invalidate_dcache_range(addr, addr + + xhci_getalignedlength(type_len)); + } + break; + } + + return; +} + +/** + * frees the "segment" pointer passed + * + * @param ptr pointer to "segement" to be freed + * @return none + */ +static void xhci_segment_free(struct xhci_segment *seg) +{ + if (seg->trbs) { + free(seg->trbs); + seg->trbs = NULL; + } + + free(seg); +} + +/** + * frees the "ring" pointer passed + * + * @param ptr pointer to "ring" to be freed + * @return none + */ +void xhci_ring_free(struct xhci_ring *ring) +{ + struct xhci_segment *seg; + struct xhci_segment *first_seg; + + if (!ring) + return; + if (ring->first_seg) { + first_seg = ring->first_seg; + seg = first_seg->next; + while (seg != first_seg) { + struct xhci_segment *next = seg->next; + xhci_segment_free(seg); + seg = next; + } + xhci_segment_free(first_seg); + ring->first_seg = NULL; + } + + free(ring); +} + +/** + * frees the "xhci_container_ctx" pointer passed + * + * @param ptr pointer to "xhci_container_ctx" to be freed + * @return none + */ +static void xhci_free_container_ctx(struct xhci_container_ctx *ctx) +{ + if (!ctx) + return; + free(ctx->bytes); + free(ctx); +} + +/** + * frees the virtual devices for "xhci_ctrl" pointer passed + * + * @param ptr pointer to "xhci_ctrl" to be freed + * @return 0 for Success freeing else 1 if the pointer or slot id is invalid. + */ +int xhci_free_virt_device(struct xhci_ctrl *ctrl) +{ + int i; + int slot_id = 0; + struct xhci_virt_device *virt_dev; + + if (!ctrl) + return -1; + + slot_id = ctrl->slot_id; + + /* Slot ID 0 is reserved */ + if (slot_id == 0 || !ctrl->devs[slot_id]) { + debug("Bad Slot ID %d\n", slot_id); + return -1; + } + + virt_dev = ctrl->devs[slot_id]; + + ctrl->dcbaa->dev_context_ptrs[slot_id] = 0; + + if (!virt_dev) + return -1; + + for (i = 0; i < 31; ++i) { + if (virt_dev->eps[i].ring) + xhci_ring_free(virt_dev->eps[i].ring); + } + + if (virt_dev->in_ctx) + xhci_free_container_ctx(virt_dev->in_ctx); + if (virt_dev->out_ctx) + xhci_free_container_ctx(virt_dev->out_ctx); + + free(ctrl->devs[slot_id]); + ctrl->devs[slot_id] = NULL; + + return 0; +} + +/** + * frees all the memory allocated + * + * @param ptr pointer to "xhci_ctrl" to be cleaned up + * @return none + */ +void xhci_cleanup(struct xhci_ctrl *ctrl) +{ + xhci_ring_free(ctrl->event_ring); + xhci_ring_free(ctrl->cmd_ring); + xhci_free_virt_device(ctrl); + free(ctrl->erst.entries); + free(ctrl->dcbaa); + memset(ctrl, '\0', sizeof(struct xhci_ctrl)); +} + +/** + * Malloc the aligned memory + * + * @param ptr pointer to "xhci_ctrl" to be cleaned up + * @return allocates the memory and returns the aligned pointer + */ +void *xhci_malloc(unsigned int size) +{ + void *ptr = memalign(XHCI_ALIGNMENT, size); + memset(ptr, '\0', size); + return ptr; +} + +/** + * Waits for as per specified amount of time + * for the "result" to match with "done" + * + * @param ptr pointer to the register to be read + * @param mask mask for the value read + * @param done value to be campared with result + * @param usec time to wait till + * @return 0 if handshake is success else -1 on failure + */ +static int handshake(uint32_t volatile *ptr, uint32_t mask, + uint32_t done, int usec) +{ + uint32_t result; + + do { + result = xhci_readl(ptr); + if (result == ~(uint32_t)0) + return -ENODEV; + result &= mask; + if (result == done) + return 0; + usec--; + udelay(1); + } while (usec > 0); + + return -ETIMEDOUT; +} + +/** + * Disable interrupts and begin the xHCI halting process. + * + * @param hcor pointer to host controller operation registers + * @return none + */ +void xhci_quiesce(struct xhci_hcor *hcor) +{ + uint32_t halted; + uint32_t cmd; + uint32_t mask; + + mask = ~(XHCI_IRQS); + halted = xhci_readl(&hcor->or_usbsts) & STS_HALT; + if (!halted) + mask &= ~CMD_RUN; + + cmd = xhci_readl(&hcor->or_usbcmd); + cmd &= mask; + xhci_writel(&hcor->or_usbcmd, cmd); +} + +/** + * Force HC into halt state. + * Disable any IRQs and clear the run/stop bit. + * HC will complete any current and actively pipelined transactions, and + * should halt within 16 ms of the run/stop bit being cleared. + * Read HC Halted bit in the status register to see when the HC is finished. + * + * @param hcor pointer to host controller operation registers + * @return status of the handshake + */ +int xhci_halt(struct xhci_hcor *hcor) +{ + int ret; + debug("Halt the HC\n"); + xhci_quiesce(hcor); + + ret = handshake(&hcor->or_usbsts, + STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); + if (ret) + debug("Host not halted after %u microseconds.\n", + XHCI_MAX_HALT_USEC); + return ret; +} + +/** + * Set the run bit and wait for the host to be running. + * + * @param hcor pointer to host controller operation registers + * @return status of the Handshake + */ +static int xhci_start(struct xhci_hcor *hcor) +{ + u32 temp; + int ret; + + printf("Starting the controller\n"); + temp = xhci_readl(&hcor->or_usbcmd); + temp |= (CMD_RUN); + xhci_writel(&hcor->or_usbcmd, temp); + temp = xhci_readl(&hcor->or_usbcmd); + + /* + * Wait for the HCHalted Status bit to be 0 to indicate the host is + * running. + */ + ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC); + if (ret) + debug("Host took too long to start, " + "waited %u microseconds.\n", + XHCI_MAX_HALT_USEC); + return ret; +} + +/** + * Resets the XHCI Controller + * + * @param hcor pointer to host controller operation registers + * @return -1 if XHCI Controller is halted else status of handshake + */ +int xhci_reset(struct xhci_hcor *hcor) +{ + u32 command; + u32 state; + int ret; + + state = xhci_readl(&hcor->or_usbsts); + if ((state & STS_HALT) == 0) { + debug("Host controller not halted, aborting reset.\n"); + return -1; + } + + debug("// Reset the HC\n"); + command = xhci_readl(&hcor->or_usbcmd); + command |= CMD_RESET; + xhci_writel(&hcor->or_usbcmd, command); + + ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC); + if (ret) + return ret; + + /* + * xHCI cannot write to any doorbells or operational registers other + * than status until the "Controller Not Ready" flag is cleared. + */ + return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC); +} + +/** + * Allocates a generic ring segment from the ring pool, sets the dma address, + * initializes the segment to zero, and sets the private next pointer to NULL. + * Section 4.11.1.1: + * "All components of all Command and Transfer TRBs shall be initialized to '0'" + * + * @param none + * @return pointer to the newly allocated SEGMENT + */ +static struct xhci_segment *xhci_segment_alloc(void) +{ + struct xhci_segment *seg; + + seg = (struct xhci_segment *)xhci_malloc(sizeof(struct xhci_segment)); + if (!seg) + return NULL; + + seg->trbs = (union xhci_trb *)xhci_malloc(SEGMENT_SIZE); + + if (!seg->trbs) + return NULL; + + seg->next = NULL; + + return seg; +} + +/** + * Make the prev segment point to the next segment. + * Change the last TRB in the prev segment to be a Link TRB which points to the + * address of the next segment. The caller needs to set any Link TRB + * related flags, such as End TRB, Toggle Cycle, and no snoop. + * + * @param prev pointer to the previous segment + * @param next pointer to the next segment + * @param link_trbs flag to indicate whether to link the trbs or NOT + * @return none + */ +static void xhci_link_segments(struct xhci_segment *prev, + struct xhci_segment *next, bool link_trbs) +{ + u32 val; + u64 val_64 = 0; + + if (!prev || !next) + return; + prev->next = next; + if (link_trbs) { + val_64 = (uintptr_t)next->trbs; + prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = val_64; + + /* + * Set the last TRB in the segment to + * have a TRB type ID of Link TRB + */ + val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); + val &= ~TRB_TYPE_BITMASK; + val |= (TRB_LINK << TRB_TYPE_SHIFT); + + /* + * Always set the chain bit with 0.95 hardware + * Set chain bit for isoc rings on AMD 0.96 host + * NOT SUPPORTING ANY QUIRK DEVICE + */ + prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); + } +} + +/** + * Initialises the Ring's enqueue,dequeue,enq_seg pointers + * + * @param ring pointer to the RING to be intialised + * @return none + */ +static void xhci_initialize_ring_info(struct xhci_ring *ring) +{ + /* + * The ring is empty, so the enqueue pointer == dequeue pointer + */ + ring->enqueue = ring->first_seg->trbs; + ring->enq_seg = ring->first_seg; + ring->dequeue = ring->enqueue; + ring->deq_seg = ring->first_seg; + + /* + * The ring is initialized to 0. The producer must write 1 to the + * cycle bit to handover ownership of the TRB, so PCS = 1. + * The consumer must compare CCS to the cycle bit to + * check ownership, so CCS = 1. + */ + ring->cycle_state = 1; + /* + * Not necessary for new rings, but needed for re-initialized rings + */ + ring->enq_updates = 0; + ring->deq_updates = 0; +} + +/** + * Create a new ring with zero or more segments. + * + * Link each segment together into a ring. + * Set the end flag and the cycle toggle bit on the last segment. + * See section 4.9.1 and figures 15 and 16. + * + * @param num_segs number of segments in the ring + * @param link_trbs flag to indicate whether to link the trbs or NOT + * @return pointer to the newly created RING + */ +static struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs) +{ + struct xhci_ring *ring; + struct xhci_segment *prev; + + ring = (struct xhci_ring *)malloc(sizeof(struct xhci_ring)); + if (!ring) + return NULL; + + if (num_segs == 0) + return ring; + + ring->first_seg = xhci_segment_alloc(); + if (!ring->first_seg) + return NULL; + num_segs--; + + prev = ring->first_seg; + while (num_segs > 0) { + struct xhci_segment *next; + + next = xhci_segment_alloc(); + if (!next) + return NULL; + xhci_link_segments(prev, next, link_trbs); + + prev = next; + num_segs--; + } + xhci_link_segments(prev, ring->first_seg, link_trbs); + if (link_trbs) { + /* See section 4.9.2.1 and 6.4.4.1 */ + prev->trbs[TRBS_PER_SEGMENT-1].link.control |= + cpu_to_le32(LINK_TOGGLE); + } + xhci_initialize_ring_info(ring); + + return ring; +} + +/** + * Checks whether the enqueue trb is a link trb or NOT + * + * @param ring pointer to the RING + * @return 1 if the enqueue TRB is the link TRB else 0 + */ +static int enqueue_is_link_trb(struct xhci_ring *ring) +{ + struct xhci_link_trb *link = &ring->enqueue->link; + + return ((link->control & cpu_to_le32(TRB_TYPE_BITMASK)) == + cpu_to_le32(TRB_LINK << TRB_TYPE_SHIFT)); +} + +/** + * Is this TRB a link TRB or was the last TRB the last TRB in this event ring + * segment? I.e. would the updated event TRB pointer step off the end of the + * event seg ? + * + * @param ctrl Host controller data structure + * @param ring pointer to the ring + * @param seg poniter to the segment to which TRB belongs + * @return 1 if this TRB a link TRB else 0 + */ +static int last_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring, + struct xhci_segment *seg, union xhci_trb *trb) +{ + if (ring == ctrl->event_ring) + return trb == &seg->trbs[TRBS_PER_SEGMENT]; + else + return ((trb->link.control & cpu_to_le32(TRB_TYPE_BITMASK)) == + cpu_to_le32(TRB_LINK << TRB_TYPE_SHIFT)); +} + +/** + * Does this link TRB point to the first segment in a ring, + * or was the previous TRB the last TRB on the last segment in the ERST? + * + * @param ctrl Host controller data structure + * @param ring pointer to the ring + * @param seg poniter to the segment to which TRB belongs + * @return 1 if this TRB is the last TRB on the last segment else 0 + */ +static bool last_trb_on_last_seg(struct xhci_ctrl *ctrl, struct xhci_ring *ring, + struct xhci_segment *seg, union xhci_trb *trb) +{ + if (ring == ctrl->event_ring) + return ((trb == &seg->trbs[TRBS_PER_SEGMENT]) && + (seg->next == ring->first_seg)); + else + return le32_to_cpu(trb->link.control) & LINK_TOGGLE; +} + +/** + * See Cycle bit rules. SW is the consumer for the event ring only. + * Don't make a ring full of link TRBs. That would be dumb and this would loop. + * + * If we've just enqueued a TRB that is in the middle of a TD (meaning the + * chain bit is set), then set the chain bit in all the following link TRBs. + * If we've enqueued the last TRB in a TD, make sure the following link TRBs + * have their chain bit cleared (so that each Link TRB is a separate TD). + * + * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit + * set, but other sections talk about dealing with the chain bit set. This was + * fixed in the 0.96 specification errata, but we have to assume that all 0.95 + * xHCI hardware can't handle the chain bit being cleared on a link TRB. + * + * @param ctrl Host controller data structure + * @param ring pointer to the ring + * @param consumer flag to indicate whether caller is consumer or producer + * @param more_trbs_coming flag to indicate whether more trbs + * are expected or NOT. + * Will you enqueue more TRBs before calling + * prepare_ring()? + * @return none + */ +static void inc_enq(struct xhci_ctrl *ctrl, struct xhci_ring *ring, + bool consumer, bool more_trbs_coming) +{ + u32 chain; + union xhci_trb *next; + + chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; + next = ++(ring->enqueue); + + ring->enq_updates++; + /* + * Update the dequeue pointer further if that was a link TRB or we're at + * the end of an event ring segment (which doesn't have link TRBS) + */ + while (last_trb(ctrl, ring, ring->enq_seg, next)) { + if (!consumer) { + if (ring != ctrl->event_ring) { + /* + * If the caller doesn't plan on enqueueing more + * TDs before ringing the doorbell, then we + * don't want to give the link TRB to the + * hardware just yet. We'll give the link TRB + * back in prepare_ring() just before we enqueue + * the TD at the top of the ring. + */ + if (!chain && !more_trbs_coming) + break; + + /* + * If we're not dealing with 0.95 hardware or + * isoc rings on AMD 0.96 host, + * carry over the chain bit of the previous TRB + * (which may mean the chain bit is cleared). + */ + next->link.control &= cpu_to_le32(~TRB_CHAIN); + next->link.control |= cpu_to_le32(chain); + + next->link.control ^= cpu_to_le32(TRB_CYCLE); + } + /* Toggle the cycle bit after the last ring segment. */ + if (last_trb_on_last_seg(ctrl, ring, + ring->enq_seg, next)) + ring->cycle_state = (ring->cycle_state ? 0 : 1); + } + ring->enq_seg = ring->enq_seg->next; + ring->enqueue = ring->enq_seg->trbs; + next = ring->enqueue; + + xhci_flush_inval_cache((uint32_t)ring->enqueue, XHCI_TRB, 1); + } +} + +/** + * Generic function for queueing a TRB on a ring. + * The caller must have checked to make sure there's room on the ring. + * + * @param more_trbs_coming: Will you enqueue more TRBs before calling + * prepare_ring()? + * @param ctrl Host controller data structure + * @param ring pointer to the ring + * @param consumer flag to indicate whether caller is consumer or producer + * @param more_trbs_coming flag to indicate whether more trbs + * @param field4 field 4 of the Generic TRB + * @return pointer to the enqueued trb + */ +static struct xhci_generic_trb *queue_trb(struct xhci_ctrl *ctrl, + struct xhci_ring *ring, + bool consumer, + bool more_trbs_coming, + u32 *trb_fields) +{ + struct xhci_generic_trb *trb; + int i; + + trb = &ring->enqueue->generic; + + for (i = 0; i < 4; i++) + trb->field[i] = cpu_to_le32(trb_fields[i]); + + xhci_flush_inval_cache((uint32_t)trb, XHCI_TRB, 1); + + inc_enq(ctrl, ring, consumer, more_trbs_coming); + + return trb; +} + +/** + * Does various checks on the endpoint ring, and makes it ready + * to queue num_trbs. + * + * @param ctrl Host controller data structure + * @param ep_ring pointer to the EP Transfer Ring + * @param ep_state State of the End Point + * @return none + */ +static int prepare_ring(struct xhci_ctrl *ctrl, struct xhci_ring *ep_ring, + u32 ep_state) +{ + /* Make sure the endpoint has been added to xHC schedule */ + switch (ep_state) { + case EP_STATE_DISABLED: + /* + * USB core changed config/interfaces without notifying us, + * or hardware is reporting the wrong state. + */ + debug("WARN urb submitted to disabled ep\n"); + return -ENOENT; + case EP_STATE_ERROR: + debug("WARN waiting for error on ep to be cleared\n"); + return -EINVAL; + case EP_STATE_HALTED: + debug("WARN halted endpoint, queueing URB anyway.\n"); + case EP_STATE_STOPPED: + case EP_STATE_RUNNING: + debug("EP STATE RUNNING.\n"); + break; + default: + debug("ERROR unknown endpoint state for ep\n"); + return -EINVAL; + } + + if (enqueue_is_link_trb(ep_ring)) { + struct xhci_ring *ring = ep_ring; + union xhci_trb *next; + + next = ring->enqueue; + + while (last_trb(ctrl, ring, ring->enq_seg, next)) { + /* + * If we're not dealing with 0.95 hardware or isoc rings + * on AMD 0.96 host, clear the chain bit. + */ + next->link.control &= cpu_to_le32(~TRB_CHAIN); + + next->link.control ^= cpu_to_le32(TRB_CYCLE); + + /* Toggle the cycle bit after the last ring segment. */ + if (last_trb_on_last_seg(ctrl, ring, + ring->enq_seg, next)) + ring->cycle_state = (ring->cycle_state ? 0 : 1); + ring->enq_seg = ring->enq_seg->next; + ring->enqueue = ring->enq_seg->trbs; + next = ring->enqueue; + } + } + + return 0; +} + +/** + * Generic function for queueing a command TRB on the command ring. + * Check to make sure there's room on the command ring for one command TRB. + * + * @param ctrl Host controller data structure + * @param trb_fields holds the field of the Generic TRB + * @return + */ +static int queue_command(struct xhci_ctrl *ctrl, u32 *trb_fields) +{ + int ret; + u32 fields[4]; + + ret = prepare_ring(ctrl, ctrl->cmd_ring, EP_STATE_RUNNING); + if (ret < 0) { + debug("ERR: No room for command on command ring\n"); + return ret; + } + + fields[0] = trb_fields[0]; + fields[1] = trb_fields[1]; + fields[2] = trb_fields[2]; + fields[3] = trb_fields[3] | ctrl->cmd_ring->cycle_state; + + queue_trb(ctrl, ctrl->cmd_ring, false, false, fields); + + xhci_flush_inval_cache((uint32_t)ctrl->cmd_ring->enqueue, XHCI_TRB, 1); + + return 0; +} + +/** + * Ring the host controller doorbell after placing a command on the ring + * + * @param ctrl Host controller data structure + * return none + */ +void xhci_ring_cmd_db(struct xhci_ctrl *ctrl) +{ + xhci_writel(&ctrl->dba->doorbell[0], DB_VALUE_HOST); + + /* Flush PCI posted writes */ + xhci_readl(&ctrl->dba->doorbell[0]); +} + +/** + * Ring the host controller doorbell after placing a command on the ring + * + * @param ctrl Host controller data structure + * @param slot_id slot id of the Device + * @param ep_index End point to be ringed + * @param stream_idx Stream ID + * return none + */ +void xhci_ring_ep_doorbell(struct xhci_ctrl *ctrl, + unsigned int slot_id, + unsigned int ep_index, + unsigned int stream_id) +{ + xhci_writel(&ctrl->dba->doorbell[slot_id], DB_VALUE(ep_index, 0)); +} + +/** + * Give the address of "trb" in the segment "seg" + * + * @param seg pointer to the Segment + * @param trb Pointer to the TRB whose address is required + * @return 0 if the TRB isn't in this segment, otherwise it returns the + * address of the TRB. + */ +unsigned long trb_addr(struct xhci_segment *seg, + union xhci_trb *trb) +{ + unsigned long segment_offset; + + if (!seg || !trb || trb < seg->trbs) + return 0; + + /* offset in TRBs */ + segment_offset = trb - seg->trbs; + if (segment_offset > TRBS_PER_SEGMENT) + return 0; + + return (unsigned long)(seg->trbs + (segment_offset * sizeof(*trb))); +} + +/** + * The TD size is the number of bytes remaining in the TD (including this TRB), + * right shifted by 10. + * It must fit in bits 21:17, so it can't be bigger than 31. + * + * @param remainder remaining packets to be sent + * @return remainder if remainder is less than max else max + */ +static u32 xhci_td_remainder(unsigned int remainder) +{ + u32 max = (1 << (21 - 17 + 1)) - 1; + + if ((remainder) >= max) + return max << 17; + else + return (remainder) << 17; +} + +/** + * Used for passing endpoint bitmasks between the core and HCDs. + * Find the index for an endpoint given its descriptor. + * Use the return value to right shift 1 for the bitmask. + * + * Index = (epnum * 2) + direction - 1, + * where direction = 0 for OUT, 1 for IN. + * For control endpoints, the IN index is used (OUT index is unused), so + * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) + * + * @param desc USB enpdoint Descriptor + * @param req Request Type + * @return index of the Endpoint + */ +unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc, + struct devrequest *req) +{ + unsigned int index; + if (req != NULL) { + index = (unsigned int)((desc->bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK)*2); + } else { + index = (unsigned int)((desc->bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK)*2) + + (((desc->bEndpointAddress & + USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) ? + 1 : 0) - 1; + } + + return index; +} + +/** + * Ring the doorbell of the End Point + * + * @param slot_id Slod id allocated by XHCI controller + * @param ep_index index of the endpoint + * @param ctrl Host controller data structure + * @param start_cycle cycle flag of the first TRB + * @param start_trb pionter to the first TRB + * @return none + */ +static void giveback_first_trb(struct xhci_ctrl *ctrl, int slot_id, + unsigned int ep_index, + unsigned int stream_id, + int start_cycle, + struct xhci_generic_trb *start_trb) +{ + int delay; + /* + * Pass all the TRBs to the hardware at once and make sure this write + * isn't reordered. + */ + if (start_cycle) + start_trb->field[3] |= cpu_to_le32(start_cycle); + else + start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); + + xhci_flush_inval_cache((uint32_t)start_trb, XHCI_TRB, 1); + + xhci_ring_ep_doorbell(ctrl, slot_id, ep_index, stream_id); + + /* + * Not a Super Speed Device , + * then give some time to Devices(FS/HS/LS) to respond + */ + delay = (ctrl->speed != USB_SPEED_SUPER) ? 110 : 1; + mdelay(delay); + + return; +} + +/** + * Gets the EP context from based on the ep_index + * + * @param ctrl Host controller data structure + * @param ctx context container + * @param ep_index index of the endpoint + * @return pointer to the End point context + */ +struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *ctx, + unsigned int ep_index) +{ + /* increment ep index by offset of start of ep ctx array */ + ep_index++; + if (ctx->type == XHCI_CTX_TYPE_INPUT) + ep_index++; + + return (struct xhci_ep_ctx *) + (ctx->bytes + + (ep_index * CTX_SIZE(readl(&ctrl->hccr->cr_hccparams)))); +} + +/** + * Handles the result of the configure endpoint Request + * + * @param ctrl Host controller data structure + * @param cmd_status status of the Event + * @return negative number if failure 0 on success + */ +static int xhci_configure_endpoint_result(struct xhci_ctrl *ctrl, + u32 *cmd_status) +{ + int ret = 0; + + switch (*cmd_status) { + case COMP_ENOMEM: + debug("Not enough host controller resources" + "for new device state.\n"); + ret = -ENOMEM; + break; + case COMP_BW_ERR: + case COMP_2ND_BW_ERR: + debug("Not enough bandwidth for new device state.\n"); + ret = -ENOSPC; + break; + case COMP_TRB_ERR: + /* the HCD set up something wrong */ + debug("ERROR: Endpoint drop flag = 0, add flag = 1," + "and endpoint is not disabled.\n"); + ret = -EINVAL; + break; + case COMP_DEV_ERR: + debug("ERROR: Incompatible device" + "for endpoint configure command.\n"); + ret = -ENODEV; + break; + case COMP_SUCCESS: + debug("Successful Endpoint Configure command\n"); + break; + default: + debug("ERROR: unexpected command completion code 0x%x.\n", + *cmd_status); + ret = -EINVAL; + break; + } + + return ret; +} + +/** + * Handles the result of the Evaluate endpoint Request + * + * @param cmd_status command status to be evaluated + * @return negative number if failure else 0 on success + */ +static int xhci_evaluate_context_result(u32 *cmd_status) +{ + int ret; + + switch (*cmd_status) { + case COMP_EINVAL: + debug("WARN: xHCI driver setup invalid evaluate" + "context command.\n"); + ret = -EINVAL; + break; + case COMP_EBADSLT: + debug("WARN: slot not enabled for evaluate" + "context command.\n"); + case COMP_CTX_STATE: + debug("WARN: invalid context state for evaluate" + "context command.\n"); + + ret = -EINVAL; + break; + case COMP_DEV_ERR: + debug("ERROR: Incompatible device for evaluate" + "context command.\n"); + ret = -ENODEV; + break; + case COMP_MEL_ERR: + /* Max Exit Latency too large error */ + debug("WARN: Max Exit Latency too large\n"); + ret = -EINVAL; + break; + case COMP_SUCCESS: + debug("Successful evaluate context command\n"); + ret = 0; + break; + default: + debug("ERROR: unexpected command completion code 0x%x.\n", + *cmd_status); + ret = -EINVAL; + break; + } + + return ret; +} + +/** + * Queue a configure endpoint command TRB + * + * @param ctrl Host controller data structure + * @param in_ctx_bytes pointer to input context + * @param slot_id slot it allocated by XHCI controller + * @return status of the queue_command + */ +int xhci_queue_configure_endpoint(struct xhci_ctrl *ctrl, u8 *in_ctx_bytes, + u32 slot_id) +{ + u64 val_64; + u32 trb_fields[4]; + + val_64 = (uintptr_t)in_ctx_bytes; + + trb_fields[0] = lower_32_bits(val_64); + trb_fields[1] = upper_32_bits(val_64); + trb_fields[2] = 0; + trb_fields[3] = ((TRB_CONFIG_EP << TRB_TYPE_SHIFT) | + ((slot_id & SLOT_ID_FOR_TRB_MASK) << + SLOT_ID_FOR_TRB_SHIFT)); + + return queue_command(ctrl, trb_fields); +} + +/** + * Queue an evaluate context command TRB + * + * @param ctrl Host controller data structure + * @param in_ctx_bytes pointer to input context + * @param slot_id slot it allocated by XHCI controller + * @return status of the queue_command + */ +int xhci_queue_evaluate_context(struct xhci_ctrl *ctrl, u8 *in_ctx_bytes, + u32 slot_id) +{ + u64 val_64; + u32 trb_fields[4]; + + val_64 = (uintptr_t)in_ctx_bytes; + + trb_fields[0] = lower_32_bits(val_64); + trb_fields[1] = upper_32_bits(val_64); + trb_fields[2] = 0; + trb_fields[3] = ((TRB_EVAL_CONTEXT << TRB_TYPE_SHIFT) | + ((slot_id & SLOT_ID_FOR_TRB_MASK) << + SLOT_ID_FOR_TRB_SHIFT)); + + return queue_command(ctrl, trb_fields); +} + +/** + * Issue a configure endpoint command or evaluate context command + * and wait for it to finish. + * + * @param usbdev pointer to the Device Data Structure + * @param ctx_change flag to indicate the Context has changed or NOT + * @return -ENOMEM if xhci_queue_configure_endpoint or + * xhci_queue_evaluate_context fails else status of + * xhci_queue_configure_endpoint or xhci_queue_evaluate_context. + */ +static int xhci_configure_endpoint(struct usb_device *usbdev, bool ctx_change) +{ + int ret; + struct xhci_container_ctx *in_ctx; + u32 *cmd_status; + struct xhci_virt_device *virt_dev; + struct xhci_ctrl *ctrl = usbdev->controller; + + virt_dev = ctrl->devs[ctrl->slot_id]; + in_ctx = virt_dev->in_ctx; + + cmd_status = &virt_dev->cmd_status; + + if (!ctx_change) + ret = xhci_queue_configure_endpoint(ctrl, in_ctx->bytes, + ctrl->slot_id); + else + ret = xhci_queue_evaluate_context(ctrl, in_ctx->bytes, + ctrl->slot_id); + + if (ret < 0) + return -ENOMEM; + + xhci_ring_cmd_db(ctrl); + + /* Give some time to the DEVICE to Respond */ + mdelay(5); + + xhci_poll_and_HandleEvent(usbdev); + + if (!ctx_change) + ret = xhci_configure_endpoint_result(ctrl, cmd_status); + else + ret = xhci_evaluate_context_result(cmd_status); + + return ret; +} + +/** + * Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. + * Useful when you want to change one particular aspect of the endpoint and then + * issue a configure endpoint command. + + * Full speed devices may have a max packet size greater than 8 bytes, but the + * USB core doesn't know that until it reads the first 8 bytes of the + * descriptor. If the usb_device's max packet size changes after that point, + * we need to issue an evaluate context command and wait on it. + * + * @param usbdev pointer to the USB device structure + * @return returns the status of the xhci_configure_endpoint + */ +static int xhci_configure_ep(struct usb_device *usbdev) +{ + struct xhci_container_ctx *in_ctx; + struct xhci_container_ctx *out_ctx; + struct xhci_input_control_ctx *ctrl_ctx; + struct xhci_slot_ctx *slot_ctx; + struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM]; + int ret = 0; + int cur_ep; + int max_ep_flag = 0; + int ep_index; + unsigned int dir; + unsigned int ep_type; + struct xhci_ctrl *ctrl = usbdev->controller; + int num_of_ep; + int ep_flag = 0; + u64 trb_64 = 0; + int slot_id = ctrl->slot_id; + struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; + struct usb_interface *ifdesc; + + out_ctx = virt_dev->out_ctx; + in_ctx = virt_dev->in_ctx; + + xhci_flush_inval_cache((uint32_t)in_ctx, XHCI_CTX, 0); + xhci_flush_inval_cache((uint32_t)out_ctx, XHCI_CTX, 0); + xhci_flush_inval_cache((uint32_t)in_ctx->bytes, in_ctx->size, 0); + xhci_flush_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size, 0); + + num_of_ep = usbdev->config.if_desc[0].no_of_ep; + ifdesc = &usbdev->config.if_desc[0]; + + /* + * STEP 1: Set up the input context flags for the command + * FIXME: This won't work if a non-default control endpoint + * changes max packet sizes. + */ + ctrl_ctx = xhci_get_input_control_ctx(ctrl->devs[slot_id]->in_ctx); + + /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */ + for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) { + ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep].ep_desc, + NULL); + ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1)); + if (max_ep_flag < ep_flag) + max_ep_flag = ep_flag; + } + ctrl_ctx->drop_flags = 0; + + /* STEP2: slot context */ + xhci_slot_copy(ctrl, in_ctx, out_ctx); + slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); + slot_ctx->dev_info &= ~(0x1f << 27); + slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0); + + xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0); + + ep_index = 0; + /* STEP4 & 5: filling up ep contexts */ + for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) { + struct usb_endpoint_descriptor *endpt_desc = NULL; + + endpt_desc = &ifdesc->ep_desc[cur_ep].ep_desc; + trb_64 = 0; + + ep_index = xhci_get_ep_index(endpt_desc, NULL); + ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); + + /* Allocate the ep rings */ + virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true); + if (!virt_dev->eps[ep_index].ring) + return -1; + + /*NOTE: ep_desc[0] actually represents EP1 and so on */ + dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7); + ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2)); + ep_ctx[ep_index]->ep_info2 = + cpu_to_le32(ep_type << EP_TYPE_SHIFT); + ep_ctx[ep_index]->ep_info2 |= + cpu_to_le32(MAX_PACKET(endpt_desc->wMaxPacketSize)); + + /* + * EP 0 can handle "burst" sizes of 1, + * so Max Burst Size field is 0 + */ + ep_ctx[ep_index]->ep_info2 |= + cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) | + ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT)); + + trb_64 = (uintptr_t) + virt_dev->eps[ep_index].ring->first_seg->trbs; + ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 | + virt_dev->eps[ep_index].ring->cycle_state); + } + + xhci_flush_inval_cache((uint32_t)virt_dev->in_ctx, XHCI_CTX, 1); + xhci_flush_inval_cache((uint32_t)virt_dev->in_ctx->bytes, + virt_dev->in_ctx->size, 1); + + ret = xhci_configure_endpoint(usbdev, false); + + return ret; +} + +/** + * Finds out the remanining packets to be sent + * + * @param usbdev pointer to the USB device structure + * @param running_total total size sent so far + * @param trb_buff_len length of the TRB Buffer + * @param total_packet_count total packet count + * @param ep_desc end point Descriptor + * @return 0 if running_total or trb_buff_len is 0, else remainder + */ +static u32 xhci_v1_0_td_remainder(struct usb_device *usbdev, int running_total, + int trb_buff_len, + unsigned int total_packet_count, + struct usb_endpoint_descriptor ep_desc) +{ + int packets_transferred; + + /* One TRB with a zero-length data packet. */ + if (running_total == 0 && trb_buff_len == 0) + return 0; + + /* + * All the TRB queueing functions don't count the current TRB in + * running_total. + */ + + if ((running_total + trb_buff_len) >= + le16_to_cpu(ep_desc.wMaxPacketSize)) + packets_transferred = (running_total + trb_buff_len) / + (le16_to_cpu(ep_desc.wMaxPacketSize)); + else + packets_transferred = 1; + + return xhci_td_remainder(total_packet_count - packets_transferred); +} + +/** + * Queues up the BULK Request + * + * @param usbdev pointer to the USB device structure + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @param length length of the buffer + * @param req request type + * @param ring Ring on which request be queued + * @param ep_index index of the End point + * @return returns 0 if successful else 0 on failure + */ +int xhci_queue_bulk_tx(struct usb_device *usbdev, unsigned long pipe, + struct xhci_ring *ring, + struct usb_endpoint_descriptor ep_desc, + struct devrequest *req, int length, void *buffer) +{ + int num_trbs = 0; + struct xhci_generic_trb *start_trb; + bool first_trb = 0; + bool more_trbs_coming = 0; + int start_cycle; + u32 field = 0; + u32 length_field = 0; + struct xhci_ctrl *ctrl = usbdev->controller; + int slot_id = ctrl->slot_id; + int ep_index = 0; + + int running_total, trb_buff_len; + unsigned int total_packet_count; + u64 addr; + u64 val_64 = 0; + u32 trb_fields[4]; + val_64 = (uintptr_t)buffer; + + num_trbs = 0; + + /* + * How much data is (potentially) left before the 64KB boundary? + * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec) + * that the buffer should not span 64KB boundary. if so + * we send request in more than 1 TRB by chaining them. + */ + running_total = TRB_MAX_BUFF_SIZE - + (lower_32_bits(val_64) & (TRB_MAX_BUFF_SIZE - 1)); + running_total &= TRB_MAX_BUFF_SIZE - 1; + + /* + * If there's some data on this 64KB chunk, or we have to send a + * zero-length transfer, we need at least one TRB + */ + if (running_total != 0 || length == 0) + num_trbs++; + + /* How many more 64KB chunks to transfer, how many more TRBs? */ + while (running_total < length) { + num_trbs++; + running_total += TRB_MAX_BUFF_SIZE; + } + + if (enqueue_is_link_trb(ring)) { + union xhci_trb *next; + next = ring->enqueue; + + while (last_trb(ctrl, ring, ring->enq_seg, next)) { + /* + * we're not dealing with 0.95 hardware or isoc rings + * on AMD 0.96 host, clear the chain bit. + */ + next->link.control &= cpu_to_le32(~TRB_CHAIN); + + next->link.control ^= cpu_to_le32(TRB_CYCLE); + + xhci_flush_inval_cache((uint32_t)next, XHCI_TRB, 1); + + /* Toggle the cycle bit after the last ring segment. */ + if (last_trb_on_last_seg(ctrl, ring, + ring->enq_seg, next)) + ring->cycle_state = (ring->cycle_state ? 0 : 1); + + ring->enq_seg = ring->enq_seg->next; + ring->enqueue = ring->enq_seg->trbs; + next = ring->enqueue; + + xhci_flush_inval_cache((uint32_t)ring->enqueue, + XHCI_TRB, 1); + } + } + + /* + * Don't give the first TRB to the hardware (by toggling the cycle bit) + * until we've finished creating all the other TRBs. The ring's cycle + * state may change as we enqueue the other TRBs, so save it too. + */ + start_trb = &ring->enqueue->generic; + start_cycle = ring->cycle_state; + + running_total = 0; + total_packet_count = DIV_ROUND_UP(length, ep_desc.wMaxPacketSize); + + ep_index = xhci_get_ep_index(&ep_desc, NULL); + /* How much data is in the first TRB? */ + /* + * How much data is (potentially) left before the 64KB boundary? + * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec) + * that the buffer should not span 64KB boundary. if so + * we send request in more than 1 TRB by chaining them. + */ + addr = val_64; + trb_buff_len = TRB_MAX_BUFF_SIZE - + (lower_32_bits(val_64) & (TRB_MAX_BUFF_SIZE - 1)); + + if (trb_buff_len > length) + trb_buff_len = length; + + first_trb = true; + + /* Queue the first TRB, even if it's zero-length */ + do { + u32 remainder = 0; + field = 0; + /* Don't change the cycle bit of the first TRB until later */ + if (first_trb) { + first_trb = false; + if (start_cycle == 0) + field |= 0x1; + } else { + field |= ring->cycle_state; + } + + /* + * Chain all the TRBs together; clear the chain bit in the last + * TRB to indicate it's the last TRB in the chain. + */ + if (num_trbs > 1) + field |= TRB_CHAIN; + + /* Only set interrupt on short packet for IN endpoints */ + if (usb_pipein(pipe)) + field |= TRB_ISP; + + /* Set the TRB length, TD size, and interrupter fields. */ + if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) < 0x100) + remainder = xhci_td_remainder(length - running_total); + else + remainder = xhci_v1_0_td_remainder(usbdev, + running_total, + trb_buff_len, + total_packet_count, + ep_desc); + + length_field = ((trb_buff_len & TRB_LEN_MASK) | + remainder | + ((0 & TRB_INTR_TARGET_MASK) << + TRB_INTR_TARGET_SHIFT)); + + if (num_trbs > 1) + more_trbs_coming = true; + else + more_trbs_coming = false; + + trb_fields[0] = lower_32_bits(addr); + trb_fields[1] = upper_32_bits(addr); + trb_fields[2] = length_field; + trb_fields[3] = field | (TRB_NORMAL << TRB_TYPE_SHIFT); + queue_trb(ctrl, ring, false, more_trbs_coming, trb_fields); + + --num_trbs; + + running_total += trb_buff_len; + + /* Give some time before Queueing further more TRBs */ + mdelay(5); + + xhci_flush_inval_cache((uint32_t)ring->enqueue, XHCI_TRB, 1); + xhci_flush_inval_cache((uint32_t)lower_32_bits(addr), + length, 1); + xhci_flush_inval_cache((uint32_t)lower_32_bits(addr), + length, 0); + + /* Calculate length for next transfer */ + addr += trb_buff_len; + trb_buff_len = length - running_total; + if (trb_buff_len > TRB_MAX_BUFF_SIZE) + trb_buff_len = TRB_MAX_BUFF_SIZE; + } while (running_total < length); + + giveback_first_trb(ctrl, slot_id, ep_index, 0, start_cycle, start_trb); + + xhci_flush_inval_cache((uint32_t)ring->enqueue, XHCI_TRB, 1); + xhci_flush_inval_cache((uint32_t)lower_32_bits(addr), length, 1); + xhci_flush_inval_cache((uint32_t)lower_32_bits(addr), length, 0); + + usbdev->act_len = length; + usbdev->status = 0; + + /* Not a Super Speed Device , give time to device to respond */ + if (ctrl->speed != USB_SPEED_SUPER) + mdelay(5); + + return 0; +} + +/** + * Queues up the Control Transfer Request + * + * @param usbdev pointer to the USB device structure + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @param length length of the buffer + * @param req request type + * @param ring Ring on which request be queued + * @param ep_index index of the End point + * @return returns 0 if successful else 0 on failure + */ +int xhci_queue_ctrl_tx(struct usb_device *usbdev, struct xhci_ring *ring, + unsigned long pipe, struct devrequest *req, + unsigned int length, unsigned int ep_index, + void *buffer) +{ + int ret; + int start_cycle; + int num_trbs; + u32 field; + u32 length_field; + u64 buf_64 = 0; + struct xhci_ring *ep_ring = ring; + struct xhci_generic_trb *start_trb; + struct xhci_ctrl *ctrl = usbdev->controller; + int slot_id = ctrl->slot_id; + u32 trb_fields[4]; + struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; + + xhci_flush_inval_cache((uint32_t)virt_dev->out_ctx, XHCI_CTX, 0); + xhci_flush_inval_cache((uint32_t)virt_dev->out_ctx->bytes, + virt_dev->out_ctx->size, 0); + xhci_flush_inval_cache((uint32_t)ring->enqueue, XHCI_TRB, 0); + + struct xhci_ep_ctx *ep_ctx = NULL; + ep_ctx = xhci_get_ep_ctx(ctrl, ctrl->devs[slot_id]->out_ctx, ep_index); + + /* 1 TRB for setup, 1 for status */ + num_trbs = 2; + /* + * Don't need to check if we need additional event data and normal TRBs, + * since data in control transfers will never get bigger than 16MB + * XXX: can we get a buffer that crosses 64KB boundaries? + */ + + if (length > 0) + num_trbs++; + + ret = prepare_ring(ctrl, ring, + le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK); + + if (ret < 0) + return ret; + + /* + * Don't give the first TRB to the hardware (by toggling the cycle bit) + * until we've finished creating all the other TRBs. The ring's cycle + * state may change as we enqueue the other TRBs, so save it too. + */ + start_trb = &ring->enqueue->generic; + start_cycle = ring->cycle_state; + + debug("start_trb %p, start_cycle %d\n", start_trb, start_cycle); + + /* Queue setup TRB - see section 6.4.1.2.1 */ + /* FIXME better way to translate setup_packet into two u32 fields? */ + field = 0; + field |= TRB_IDT | (TRB_SETUP << TRB_TYPE_SHIFT); + if (start_cycle == 0) + field |= 0x1; + + /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ + if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) == 0x100) { + if (length > 0) { + if (req->requesttype & USB_DIR_IN) + field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT); + else + field |= (TRB_DATA_OUT << TRB_TX_TYPE_SHIFT); + } + } + + debug("req->requesttype = %d, req->request = %d," + "le16_to_cpu(req->value) = %d," + "le16_to_cpu(req->index) = %d," + "le16_to_cpu(req->length) = %d\n", + req->requesttype, req->request, le16_to_cpu(req->value), + le16_to_cpu(req->index), le16_to_cpu(req->length)); + + trb_fields[0] = req->requesttype | req->request << 8 | + le16_to_cpu(req->value) << 16; + trb_fields[1] = le16_to_cpu(req->index) | + le16_to_cpu(req->length) << 16; + /* TRB_LEN | (TRB_INTR_TARGET) */ + trb_fields[2] = (8 | ((0 & TRB_INTR_TARGET_MASK) << + TRB_INTR_TARGET_SHIFT)); + /* Immediate data in pointer */ + trb_fields[3] = field; + queue_trb(ctrl, ring, false, true, trb_fields); + + xhci_flush_inval_cache((uint32_t)ring->enqueue, XHCI_TRB, 1); + + mdelay(1); + + /* Re-initializing field to zero */ + field = 0; + /* If there's data, queue data TRBs */ + /* Only set interrupt on short packet for IN endpoints */ + if (usb_pipein(pipe)) + field = TRB_ISP | (TRB_DATA << TRB_TYPE_SHIFT); + else + field = (TRB_DATA << TRB_TYPE_SHIFT); + + length_field = (length & TRB_LEN_MASK) | xhci_td_remainder(length) | + ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT); + debug("length_field = %d, length = %d," + "xhci_td_remainder(length) = %d , TRB_INTR_TARGET(0) = %d\n", + length_field, (length & TRB_LEN_MASK), + xhci_td_remainder(length), 0); + + if (length > 0) { + if (req->requesttype & USB_DIR_IN) + field |= TRB_DIR_IN; + buf_64 = (uintptr_t)buffer; + + trb_fields[0] = lower_32_bits(buf_64); + trb_fields[1] = upper_32_bits(buf_64); + trb_fields[2] = length_field; + trb_fields[3] = field | ep_ring->cycle_state; + queue_trb(ctrl, ring, false, true, trb_fields); + + mdelay(1); + + xhci_flush_inval_cache((uint32_t)ring->enqueue, XHCI_TRB, 1); + xhci_flush_inval_cache((uint32_t)lower_32_bits(buf_64), + length, 0); + } + + /* + * Queue status TRB - + * see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 + */ + + /* If the device sent data, the status stage is an OUT transfer */ + field = 0; + if (length > 0 && req->requesttype & USB_DIR_IN) + field = 0; + else + field = TRB_DIR_IN; + + trb_fields[0] = 0; + trb_fields[1] = 0; + trb_fields[2] = ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT); + /* Event on completion */ + trb_fields[3] = field | TRB_IOC | + (TRB_STATUS << TRB_TYPE_SHIFT) | + ep_ring->cycle_state; + + queue_trb(ctrl, ring, false, false, trb_fields); + + xhci_flush_inval_cache((uint32_t)ring->enqueue, XHCI_TRB, 1); + xhci_flush_inval_cache((uint32_t)virt_dev->out_ctx, XHCI_CTX, 1); + xhci_flush_inval_cache((uint32_t)virt_dev->out_ctx->bytes, + virt_dev->out_ctx->size, 1); + + mdelay(1); + + giveback_first_trb(ctrl, slot_id, ep_index, 0, start_cycle, start_trb); + + xhci_flush_inval_cache((uint32_t)ring->enqueue, XHCI_TRB, 1); + xhci_flush_inval_cache((uint32_t)lower_32_bits(buf_64), length, 0); + + usbdev->act_len = length; + usbdev->status = 0; + + /* Not a Super Speed Device , give time to device to respond */ + if (ctrl->speed != USB_SPEED_SUPER) + mdelay(5); + + return 0; +} + +/** + * Submits the asynchronous Control Requests to XHCI Host controller + * + * @param usbdev pointer to the USB device structure + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @param length length of the buffer + * @param req request type + * @return returns 0 if successful else 0 on failure + * + */ +int xhci_submit_async(struct usb_device *usbdev, + unsigned long pipe, void *buffer, + int length, struct devrequest *req) +{ + struct xhci_ctrl *ctrl = usbdev->controller; + unsigned int slot_id; + unsigned int ep_index; + int ret; + struct usb_endpoint_descriptor ep_descIN; + struct usb_endpoint_descriptor ep_descOUT; + struct usb_endpoint_descriptor ep_desc; + struct xhci_ring *ep_txring; + int cur_ep; + struct usb_interface *ifdesc; + struct xhci_virt_device *virt_dev; + struct xhci_container_ctx *out_ctx; + struct xhci_container_ctx *in_ctx; + + ifdesc = &usbdev->config.if_desc[0]; + + debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", usbdev, pipe, + buffer, length, req); + if (req != NULL) + debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", + req->request, req->request, + req->requesttype, req->requesttype, + le16_to_cpu(req->value), le16_to_cpu(req->value), + le16_to_cpu(req->index)); + + slot_id = ctrl->slot_id; + + if (ctrl->slot_id == 0) { + debug("SLOT-ID IS NOT ALLOCATED YET\n"); + usbdev->act_len = 21; + usbdev->status = 0; + return 0; + } + + virt_dev = ctrl->devs[slot_id]; + in_ctx = virt_dev->in_ctx; + out_ctx = virt_dev->out_ctx; + + if (usb_pipecontrol(pipe) && req != NULL) { + /* + * Check to see if the max packet size for the default control + * endpoint changed during FS device enumeration + */ + ep_index = 0; + ret = xhci_queue_ctrl_tx(usbdev, + ctrl->devs[slot_id]->eps[ep_index].ring, + pipe, req, length, ep_index, buffer); + if (ret) + return -1; + } else if (usb_pipebulk(pipe) && req == NULL) { + + xhci_flush_inval_cache((uint32_t)in_ctx, XHCI_CTX, 0); + xhci_flush_inval_cache((uint32_t)out_ctx, XHCI_CTX, 0); + xhci_flush_inval_cache((uint32_t)in_ctx->bytes, + in_ctx->size, 0); + xhci_flush_inval_cache((uint32_t)out_ctx->bytes, + out_ctx->size, 0); + + for (cur_ep = 0; cur_ep < ifdesc->no_of_ep; cur_ep++) { + struct usb_endpoint_descriptor epdesc; + + epdesc = ifdesc->ep_desc[cur_ep].ep_desc; + if (usb_endpoint_is_bulk_in(&epdesc)) + ep_descIN = epdesc; + else if (usb_endpoint_is_bulk_out(&epdesc)) + ep_descOUT = epdesc; + else + BUG(); + } + + if (usb_pipein(pipe)) + ep_desc = ep_descIN; + else if (usb_pipeout(pipe)) + ep_desc = ep_descOUT; + else + BUG(); + + ep_index = xhci_get_ep_index(&ep_desc, req); + ep_txring = ctrl->devs[slot_id]->eps[ep_index].ring; + ret = xhci_queue_bulk_tx(usbdev, pipe, ep_txring, + ep_desc, req, length, buffer); + if (ret) + return -1; + } + + return 0; +} + +/** + * Clears the Change bits of the Port Status Register + * + * @param wValue request value + * @param wIndex request index + * @param addr address of posrt status register + * @param port_status state of port status register + * @return none + */ +static void xhci_clear_port_change_bit(u16 wValue, + u16 wIndex, uint32_t *addr, u32 port_status) +{ + char *port_change_bit; + u32 status; + + switch (wValue) { + case USB_PORT_FEAT_C_RESET: + status = PORT_RC; + port_change_bit = "reset"; + break; + case USB_PORT_FEAT_C_CONNECTION: + status = PORT_CSC; + port_change_bit = "connect"; + break; + case USB_PORT_FEAT_C_OVER_CURRENT: + status = PORT_OCC; + port_change_bit = "over-current"; + break; + case USB_PORT_FEAT_C_ENABLE: + status = PORT_PEC; + port_change_bit = "enable/disable"; + break; + case USB_PORT_FEAT_C_SUSPEND: + status = PORT_PLC; + port_change_bit = "suspend/resume"; + break; + default: + /* Should never happen */ + return; + } + + /* Change bits are all write 1 to clear */ + xhci_writel(addr, port_status | status); + + port_status = xhci_readl(addr); + debug("clear port %s change, actual port %d status = 0x%x\n", + port_change_bit, wIndex, port_status); +} + +/** + * Save Read Only (RO) bits and save read/write bits where + * writing a 0 clears the bit and writing a 1 sets the bit (RWS). + * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. + * + * @param state state of the Port Status and Control Regsiter + * @return a value that would result in the port being in the + * same state, if the value was written to the port + * status control register. + */ +u32 xhci_port_state_to_neutral(u32 state) +{ + /* Save read-only status and port state */ + return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); +} + +/** + * Gets the Speed as per the Port Status + * @param usbdev pointer to USB device structure + * @param port_status state of port status register + * @return bit-set for usb speed for corresponding state of + * port status register + */ +static unsigned int xhci_port_speed(struct usb_device *usbdev, + unsigned int port_status) +{ + struct xhci_ctrl *ctrl = usbdev->controller; + + if (DEV_FULLSPEED(port_status)) { + usbdev->speed = 0; + debug("SPEED = FULLSPEED\n"); + ctrl->speed = usbdev->speed; + return 0x1; + } + if (DEV_LOWSPEED(port_status)) { + debug("SPEED = LOWSPEED\n"); + usbdev->speed = 1; + ctrl->speed = usbdev->speed; + return 0x2; + } + if (DEV_HIGHSPEED(port_status)) { + debug("SPEED = HIGHSPEED\n"); + usbdev->speed = 2; + ctrl->speed = usbdev->speed; + return 0x3; + } + if (DEV_SUPERSPEED(port_status)) { + debug("SPEED = SUPERSPEED\n"); + usbdev->speed = 3; + ctrl->speed = usbdev->speed; + return 0x4; + } + + return 0; +} + +/** + * Submits the Requests to the XHCI Host Controller + * + * @param usbdev pointer to the USB device structure + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @param length length of the buffer + * @return returns 0 if successful else -1 on failure + */ +int xhci_submit_root(struct usb_device *usbdev, unsigned long pipe, + void *buffer, int length, struct devrequest *req) +{ + uint8_t tmpbuf[4]; + u16 typeReq; + void *srcptr = NULL; + int len, srclen; + uint32_t reg; + uint32_t *status_reg; + struct xhci_ctrl *ctrl = usbdev->controller; + struct xhci_hcor *hcor = ctrl->hcor; + + if (le16_to_cpu(req->index) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) { + printf("The request port(%d) is not configured\n", + le16_to_cpu(req->index) - 1); + return -1; + } + + status_reg = (uint32_t *) + (&hcor->PortRegs[le16_to_cpu(req->index) - 1].or_portsc); + srclen = 0; + + typeReq = req->request | req->requesttype << 8; + + switch (typeReq) { + case DeviceRequest | USB_REQ_GET_DESCRIPTOR: + switch (le16_to_cpu(req->value) >> 8) { + case USB_DT_DEVICE: + debug("USB_DT_DEVICE request\n"); + srcptr = &descriptor.device; + srclen = 0x12; + break; + case USB_DT_CONFIG: + debug("USB_DT_CONFIG config\n"); + srcptr = &descriptor.config; + srclen = 0x19; + break; + case USB_DT_STRING: + debug("USB_DT_STRING config\n"); + switch (le16_to_cpu(req->value) & 0xff) { + case 0: /* Language */ + srcptr = "\4\3\1\0"; + srclen = 4; + break; + case 1: /* Vendor String */ + srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; + srclen = 14; + break; + case 2: /* Product Name */ + srcptr = "\52\3X\0H\0C\0I\0 " + "\0H\0o\0s\0t\0 " + "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; + srclen = 42; + break; + default: + debug("unknown value DT_STRING %x\n", + le16_to_cpu(req->value)); + goto unknown; + } + break; + default: + debug("unknown value %x\n", le16_to_cpu(req->value)); + goto unknown; + } + break; + case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): + switch (le16_to_cpu(req->value) >> 8) { + case USB_DT_HUB: + debug("USB_DT_HUB config\n"); + srcptr = &descriptor.hub; + srclen = 0x8; + break; + default: + debug("unknown value %x\n", le16_to_cpu(req->value)); + goto unknown; + } + break; + case USB_REQ_ALLOC_DEV | (USB_RECIP_DEVICE << 8): + xhci_alloc_dev(usbdev); + break; + case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): + if (usbdev->devnum == 1) + ctrl->rootdev = le16_to_cpu(req->value); + else + xhci_address_device(usbdev); + break; + case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: + /* FIXME: need to put code for configuring endpoint here */ + xhci_configure_ep(usbdev); + break; + case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): + tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ + tmpbuf[1] = 0; + srcptr = tmpbuf; + srclen = 2; + break; + case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): + memset(tmpbuf, 0, 4); + reg = xhci_readl(status_reg); + if (reg & PORT_CONNECT) { + tmpbuf[0] |= USB_PORT_STAT_CONNECTION; + tmpbuf[1] |= (xhci_port_speed(usbdev, reg) << 2); + } + if (reg & PORT_PE) + tmpbuf[0] |= USB_PORT_STAT_ENABLE; + if (reg & XDEV_U3) + tmpbuf[0] |= USB_PORT_STAT_SUSPEND; + if (reg & PORT_OC) + tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; + if (reg & PORT_RESET) + tmpbuf[0] |= USB_PORT_STAT_RESET; + if (reg & PORT_POWER) + tmpbuf[1] |= USB_SS_PORT_STAT_POWER >> 8; + if ((reg & PORT_PLC)) + tmpbuf[2] |= USB_PORT_STAT_C_LINK_STATE; + if ((reg & PORT_WRC)) + tmpbuf[2] |= USB_PORT_STAT_C_BH_RESET; + if (reg & PORT_CSC) + tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; + if (reg & PORT_PEC) + tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; + if (reg & PORT_OCC) + tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; + if (reg & PORT_RC) + tmpbuf[2] |= USB_PORT_STAT_C_RESET; + + srcptr = tmpbuf; + srclen = 4; + break; + case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): + reg = xhci_readl(status_reg); + switch (le16_to_cpu(req->value)) { + case USB_PORT_FEAT_ENABLE: + reg |= PORT_PE; + xhci_writel(status_reg, reg); + break; + case USB_PORT_FEAT_POWER: + reg |= PORT_POWER; + xhci_writel(status_reg, reg); + break; + case USB_PORT_FEAT_RESET: + reg = xhci_readl(status_reg); + reg |= PORT_RESET; + xhci_writel(status_reg, reg); + xhci_poll_and_HandleEvent(usbdev); + break; + default: + debug("unknown feature %x\n", le16_to_cpu(req->value)); + goto unknown; + } + /* unblock posted writes */ + xhci_readl(&hcor->or_usbcmd); + break; + case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): + reg = xhci_readl(status_reg); + reg = xhci_port_state_to_neutral(reg); + switch (le16_to_cpu(req->value)) { + case USB_PORT_FEAT_ENABLE: + reg &= ~PORT_PE; + break; + case USB_PORT_FEAT_C_RESET: + case USB_PORT_FEAT_C_CONNECTION: + case USB_PORT_FEAT_C_OVER_CURRENT: + case USB_PORT_FEAT_C_ENABLE: + xhci_clear_port_change_bit((le16_to_cpu(req->value)), + le16_to_cpu(req->index), + status_reg, reg); + break; + default: + goto unknown; + } + xhci_writel(status_reg, reg); + /* unblock posted write */ + xhci_readl(&hcor->or_usbcmd); + break; + default: + debug("Unknown request\n"); + goto unknown; + } + + mdelay(5); + + debug("scrlen = %d\n req->length = %d\n, length = %d\n", + srclen, le16_to_cpu(req->length), length); + + len = min3(srclen, le16_to_cpu(req->length), length); + + if (srcptr != NULL && len > 0) + memcpy(buffer, srcptr, len); + else + debug("Len is 0\n"); + + usbdev->act_len = len; + usbdev->status = 0; + + return 0; + +unknown: + usbdev->act_len = 0; + usbdev->status = USB_ST_STALLED; + + return -1; +} + +/** + * Allocates the Container context + * + * @param ctrl Host controller data structure + * @param type type of Context + * @return NULL if fialed else pointer to the context on success + */ +static struct +xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_ctrl *ctrl, + int type) +{ + struct xhci_container_ctx *ctx; + + ctx = (struct xhci_container_ctx *) + xhci_malloc(sizeof(struct xhci_container_ctx)); + + if (!ctx) + return NULL; + + BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)); + ctx->type = type; + ctx->size = HCC_64BYTE_CONTEXT(readl(&ctrl->hccr->cr_hccparams)) ? + 2048 : 1024; + if (type == XHCI_CTX_TYPE_INPUT) + ctx->size += CTX_SIZE(readl(&ctrl->hccr->cr_hccparams)); + + ctx->bytes = (u8 *)xhci_malloc(ctx->size); + + return ctx; +} + +/** + * Give the input control context for the passed container context + * + * @param ctx pointer to the context + * @return pointer to the Input control context data + */ +struct xhci_input_control_ctx *xhci_get_input_control_ctx( + struct xhci_container_ctx *ctx) +{ + BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT); + return (struct xhci_input_control_ctx *)ctx->bytes; +} + +/** + * Give the slot context for the passed container context + * + * @param ctx pointer to the context + * @param ctrl Host controller data structure + * @return pointer to the slot control context data + */ +struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *ctx) +{ + if (ctx->type == XHCI_CTX_TYPE_DEVICE) + return (struct xhci_slot_ctx *)ctx->bytes; + + return (struct xhci_slot_ctx *) + (ctx->bytes + CTX_SIZE(readl(&ctrl->hccr->cr_hccparams))); +} + +/** + * See Cycle bit rules. SW is the consumer for the event ring only. + * Don't make a ring full of link TRBs. That would be dumb and this would loop. + * + * @param ctrl Host controller data structure + * @param ring Ring whose Dequeue TRB pointer needs to be incremented. + * @param consumer flag to indicate whether S/W is consumer of this RING or NOT + * return none + */ +static void inc_deq(struct xhci_ctrl *ctrl, struct xhci_ring *ring, + bool consumer) +{ + union xhci_trb *next = ++(ring->dequeue); + + ring->deq_updates++; + /* + * Update the dequeue pointer further if that was a link TRB or we're at + * the end of an event ring segment (which doesn't have link TRBS) + */ + while (last_trb(ctrl, ring, ring->deq_seg, next)) { + if (consumer && + last_trb_on_last_seg(ctrl, ring, ring->deq_seg, next)) + ring->cycle_state = (ring->cycle_state ? 0 : 1); + + ring->deq_seg = ring->deq_seg->next; + ring->dequeue = ring->deq_seg->trbs; + next = ring->dequeue; + } + + xhci_flush_inval_cache((uint32_t)ring->dequeue, XHCI_TRB, 1); +} + +/** + * Handles the port status event + * + * @param ctrl Host controller data structure + * @param event event genrated by the XHCI controller + * @return none + */ +static void handle_port_status(struct xhci_ctrl *ctrl, union xhci_trb *event) +{ + int max_ports; + + /* Port status change events always have a successful completion code */ + if (((le32_to_cpu(event->generic.field[2]) & + COMP_CODE_MASK) >> COMP_CODE_SHIFT) != COMP_SUCCESS) + return; + + ctrl->port_id = (((le32_to_cpu(event->generic.field[0]) & + PORT_ID_MASK) >> PORT_ID_SHIFT)); + + max_ports = ((readl(&ctrl->hccr->cr_hcsparams1) & + HCS_MAX_PORTS_MASK) >> HCS_MAX_PORTS_SHIFT); + + if ((ctrl->port_id <= 0) || (ctrl->port_id > max_ports)) + debug("Invalid port id %d\n", ctrl->port_id); + + return; +} + +/** + * Handles the command completion Event + * + * @param ctrl Host controller data structure + * @param event Event generated by the XHCI controller + * @return none + */ +static void handle_cmd_completion(struct xhci_ctrl *ctrl, + struct xhci_event_cmd *event) +{ + int slot_id = ((le32_to_cpu(event->flags) & + TRB_TO_SLOT_ID_MASK) >> TRB_TO_SLOT_ID_SHIFT); + u64 cmd_addr; + unsigned long cmd_dequeue_addr; + + xhci_flush_inval_cache((uint32_t)ctrl->cmd_ring->dequeue, XHCI_TRB, 0); + + cmd_addr = le64_to_cpu(event->cmd_trb); + cmd_dequeue_addr = trb_addr(ctrl->cmd_ring->deq_seg, + ctrl->cmd_ring->dequeue); + + /* Is the command ring deq ptr out of sync with the deq seg ptr? */ + if (cmd_dequeue_addr == 0) + return; + + /* + * Does the cmd trb's address match our internal + * dequeue pointer address? + */ + if (cmd_addr != (u64) cmd_dequeue_addr) + return; + + switch ((le32_to_cpu(ctrl->cmd_ring->dequeue->generic.field[3]) & + TRB_TYPE_BITMASK) >> TRB_TYPE_SHIFT) { + case TRB_ENABLE_SLOT: + if (((le32_to_cpu(event->status) & + COMP_CODE_MASK) >> COMP_CODE_SHIFT) == COMP_SUCCESS) + ctrl->slot_id = slot_id; + else + ctrl->slot_id = 0; + break; + + case TRB_ADDR_DEV: + ctrl->devs[slot_id]->cmd_status = ((le32_to_cpu(event->status) & + COMP_CODE_MASK) >> + COMP_CODE_SHIFT); + break; + + case TRB_RESET_DEV: + debug("Completed reset device command.\n"); + break; + + case TRB_EVAL_CONTEXT: + ctrl->devs[slot_id]->cmd_status = + GET_COMP_CODE(le32_to_cpu(event->status)); + break; + + case TRB_CONFIG_EP: + debug("Configure Endpoint command completed .\n"); + break; + default: + /* Skip over unknown commands on the event ring */ + break; + } + + inc_deq(ctrl, ctrl->cmd_ring, false); +} + +/** + * This function handles all CPU-owned events on the event ring. + * + * @param ctrl Host controller data structure + * @return 1 incase of success or -1 on failure + */ +static int xhci_handle_event(struct xhci_ctrl *ctrl) +{ + union xhci_trb *event; + int update_ptrs = 1; + unsigned long deq; + u64 temp_64; + + if (!ctrl->event_ring || !ctrl->event_ring->dequeue) + return -1; + + xhci_flush_inval_cache((uint32_t)ctrl->event_ring->dequeue, + XHCI_TRB, 0); + + event = ctrl->event_ring->dequeue; + + /* FIXME: Handle more event types. */ + switch ((le32_to_cpu(event->event_cmd.flags) & + TRB_TYPE_BITMASK) >> TRB_TYPE_SHIFT) { + case TRB_COMPLETION: + handle_cmd_completion(ctrl, &event->event_cmd); + debug("Handling commanding completion\n"); + break; + + case TRB_PORT_STATUS: + handle_port_status(ctrl, event); + break; + default: + if ((le32_to_cpu(event->event_cmd.flags) & + TRB_TYPE_BITMASK) == 0) + update_ptrs = 0; + break; + } + + if (update_ptrs) { + debug("Upadting dequeue pointer\n"); + /* Update SW event ring dequeue pointer */ + inc_deq(ctrl, ctrl->event_ring, true); + } + + xhci_flush_inval_cache((uint32_t)ctrl->event_ring->dequeue, + XHCI_TRB, 0); + + temp_64 = xhci_readl_64(&ctrl->ir_set->erst_dequeue); + /* If necessary, update the HW's version of the event ring deq ptr. */ + deq = (u32)(ctrl->event_ring->dequeue); + + xhci_flush_inval_cache((uint32_t)deq, XHCI_TRB, 1); + + if (deq == 0) + debug("WARN something wrong with SW event " + "ring dequeue ptr.\n"); + + /* Update HC event ring dequeue pointer */ + temp_64 &= ERST_PTR_MASK; + temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); + + /* Clear the event handler busy flag (RW1C); event ring is empty. */ + temp_64 |= ERST_EHB; + xhci_writel_64(&ctrl->ir_set->erst_dequeue, temp_64); + + return 1; +} + +/** + * Checks the ownership of the Event Command + * + * @param ctrl Host controller data structure + * @return 0 if failure else 0 on success + */ +static int xhci_check_ownership(struct xhci_ctrl *ctrl) +{ + union xhci_trb *event; + + if (!ctrl->event_ring || !ctrl->event_ring->dequeue) + return 0; + + xhci_flush_inval_cache((uint32_t)ctrl->event_ring->dequeue, + XHCI_TRB, 0); + + event = ctrl->event_ring->dequeue; + /* Does the HC or OS own the TRB? */ + if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != + ctrl->event_ring->cycle_state) + return 0; + + return 1; +} + +/** + * Checks the ownership of the Event Command + * + * @param ctrl Host controller data structure + * @return ownership flag + */ +int xhci_poll(struct xhci_ctrl *ctrl) +{ + return xhci_check_ownership(ctrl); +} + +/** + * Queue a slot enable or disable request on the command ring + * + * @param ctrl Host controller data structure + * @param trb_type type of TRB to be queued in + * @param slot_id slot id allocated by the XHCI controller + * @return status of the "queue_command" + */ +int xhci_queue_slot_control(struct xhci_ctrl *ctrl, u32 trb_type, u32 slot_id) +{ + + u32 trb_fields[4]; + + trb_fields[0] = 0; + trb_fields[1] = 0; + trb_fields[2] = 0; + trb_fields[3] = ((trb_type << TRB_TYPE_SHIFT) | + ((slot_id & SLOT_ID_FOR_TRB_MASK) << + SLOT_ID_FOR_TRB_SHIFT)); + + return queue_command(ctrl, trb_fields); +} + +/** + * Allocating virtual device + * + * @param usbdev pointer to USB deivce structure + * @param slot_id slot id allocated by the XHCI controller + * @return 0 on success else -1 on failure + */ +int xhci_alloc_virt_device(struct usb_device *usbdev, int slot_id) +{ + u64 byte_64 = 0; + struct xhci_virt_device *virt_dev; + struct xhci_ctrl *ctrl = usbdev->controller; + + /* Slot ID 0 is reserved */ + if (slot_id == 0 || ctrl->devs[slot_id]) { + debug("Bad Slot ID %d\n", slot_id); + return -1; + } + + ctrl->devs[slot_id] = (struct xhci_virt_device *) + malloc(sizeof(struct xhci_virt_device)); + + if (!ctrl->devs[slot_id]) { + debug("Failed to allocate virtual device\n"); + return -1; + } + + memset(ctrl->devs[slot_id], 0, sizeof(struct xhci_virt_device)); + virt_dev = ctrl->devs[slot_id]; + + /* Allocate the (output) device context that will be used in the HC. */ + virt_dev->out_ctx = xhci_alloc_container_ctx(ctrl, + XHCI_CTX_TYPE_DEVICE); + if (!virt_dev->out_ctx) { + debug("Failed to allocate out context for virt dev\n"); + return -1; + } + + /* Allocate the (input) device context for address device command */ + virt_dev->in_ctx = xhci_alloc_container_ctx(ctrl, + XHCI_CTX_TYPE_INPUT); + if (!virt_dev->in_ctx) { + debug("Failed to allocate in context for virt dev\n"); + return -1; + } + + /* Allocate endpoint 0 ring */ + virt_dev->eps[0].ring = xhci_ring_alloc(1, true); + if (!virt_dev->eps[0].ring) { + debug("Failed to allocate EP(0) ring\n"); + return -1; + } + + byte_64 = (uintptr_t)(virt_dev->out_ctx->bytes); + + /* Point to output device context in dcbaa. */ + ctrl->dcbaa->dev_context_ptrs[slot_id] = byte_64; + + xhci_flush_inval_cache((uint32_t) + &ctrl->dcbaa->dev_context_ptrs[slot_id], + sizeof(__le64), 1); + return 0; +} + +/** + * Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. + * Useful when you want to change one particular aspect of the endpoint + * and then issue a configure endpoint command. + * + * @param ctrl Host controller data structure + * @param in_ctx contains the inpout context + * @param out_ctx contains the inpout context + * @param ep_index index of the end point + * @return none + */ +void xhci_endpoint_copy(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *in_ctx, + struct xhci_container_ctx *out_ctx, + unsigned int ep_index) +{ + struct xhci_ep_ctx *out_ep_ctx; + struct xhci_ep_ctx *in_ep_ctx; + + out_ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index); + in_ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); + + in_ep_ctx->ep_info = out_ep_ctx->ep_info; + in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; + in_ep_ctx->deq = out_ep_ctx->deq; + in_ep_ctx->tx_info = out_ep_ctx->tx_info; +} + +/** + * Copy output xhci_slot_ctx to the input xhci_slot_ctx. + * Useful when you want to change one particular aspect of the endpoint + * and then issue a configure endpoint command. + * Only the context entries field matters, but + * we'll copy the whole thing anyway. + * + * @param ctrl Host controller data structure + * @param in_ctx contains the inpout context + * @param out_ctx contains the inpout context + * @return none + */ +void xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx, + struct xhci_container_ctx *out_ctx){ + + struct xhci_slot_ctx *in_slot_ctx; + struct xhci_slot_ctx *out_slot_ctx; + + in_slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); + out_slot_ctx = xhci_get_slot_ctx(ctrl, out_ctx); + + in_slot_ctx->dev_info = out_slot_ctx->dev_info; + in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; + in_slot_ctx->tt_info = out_slot_ctx->tt_info; + in_slot_ctx->dev_state = out_slot_ctx->dev_state; +} + +/** + * Queue an address device command TRB + * + * @param ctrl Host controller data structure + * @param in_ctx_ptr + * @param slot_id + * @return status of the "queue_command" + */ +int xhci_queue_address_device(struct xhci_ctrl *ctrl, u8 *in_ctx_ptr, + u32 slot_id) +{ + u64 val_64 = 0; + u32 trb_fields[4]; + + val_64 = (uintptr_t)in_ctx_ptr; + trb_fields[0] = lower_32_bits(val_64); + trb_fields[1] = upper_32_bits(val_64); + trb_fields[2] = 0; + trb_fields[3] = ((TRB_ADDR_DEV << TRB_TYPE_SHIFT) | + ((slot_id & SLOT_ID_FOR_TRB_MASK) << + SLOT_ID_FOR_TRB_SHIFT)); + + return queue_command(ctrl, trb_fields); +} + +/** + * Copies the EP O Transfer ring to Input Context + * + * @param ctrl Host controller data structure + * @return none + */ +void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_ctrl *ctrl) +{ + struct xhci_virt_device *virt_dev; + struct xhci_ep_ctx *ep0_ctx; + struct xhci_ring *ep_ring; + + virt_dev = ctrl->devs[ctrl->slot_id]; + ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0); + ep_ring = virt_dev->eps[0].ring; + /* + * FIXME we don't keep track of the dequeue pointer very well after a + * Set TR dequeue pointer, so we're setting the dequeue pointer of the + * host to our enqueue pointer. This should only be called after a + * configured device has reset, so all control transfers should have + * been completed or cancelled before the reset. + */ + ep0_ctx->deq = cpu_to_le64(trb_addr(ep_ring->enq_seg, + ep_ring->enqueue) | ep_ring->cycle_state); +} + +/** + * Setup an xHCI virtual device for a Set Address command + * + * @param usbdev pointer to the Device Data Structure + * @return returns negative value on failure else 0 on success + */ +int xhci_setup_addressable_virt_dev(struct usb_device *usbdev) +{ + struct xhci_virt_device *virt_dev; + struct xhci_ep_ctx *ep0_ctx; + struct xhci_slot_ctx *slot_ctx; + u32 port_num = 0; + u64 trb_64 = 0; + + struct xhci_ctrl *ctrl = usbdev->controller; + + virt_dev = ctrl->devs[ctrl->slot_id]; + + /* Slot ID 0 is reserved */ + if (ctrl->slot_id == 0 || !virt_dev) { + debug("Slot ID %d is not assigned to this device\n", + ctrl->slot_id); + return -EINVAL; + } + + /* Extract the EP0 and Slot Ctrl */ + ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0); + slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx); + + /* 3) Only the control endpoint is valid - one endpoint context */ + slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | 0); + + switch (ctrl->speed) { + + case USB_SPEED_SUPER: + slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS); + break; + case USB_SPEED_HIGH: + slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS); + break; + case USB_SPEED_FULL: + slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS); + break; + case USB_SPEED_LOW: + slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS); + break; + default: + /* Speed was set earlier, this shouldn't happen. */ + BUG(); + } + + port_num = ctrl->port_id; + debug("port_num = %d\n", port_num); + + slot_ctx->dev_info2 |= + cpu_to_le32(((port_num & ROOT_HUB_PORT_MASK) << + ROOT_HUB_PORT_SHIFT)); + + /* Step 4 - ring already allocated */ + /* Step 5 */ + ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT); + /* + * XXX: Not sure about wireless USB devices. + */ + debug("SPEED = %d\n", ctrl->speed); + + switch (ctrl->speed) { + case USB_SPEED_SUPER: + ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) << + MAX_PACKET_SHIFT)); + debug("Setting Packet size = 512bytes\n"); + break; + case USB_SPEED_HIGH: + /* USB core guesses at a 64-byte max packet first for FS devices */ + case USB_SPEED_FULL: + ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) << + MAX_PACKET_SHIFT)); + debug("Setting Packet size = 64bytes\n"); + break; + case USB_SPEED_LOW: + ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) << + MAX_PACKET_SHIFT)); + debug("Setting Packet size = 8bytes\n"); + break; + default: + /* New speed? */ + BUG(); + } + + /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ + ep0_ctx->ep_info2 |= + cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) | + ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT)); + + trb_64 = (uintptr_t)virt_dev->eps[0].ring->first_seg->trbs; + ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state); + + /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ + + return 0; +} + +/** + * Polls the XHCI controller + * and Handles the Event generated by the XHCI Controller + * + * @param usbdev pointer to the Device Data Structure + * @return none + */ +void xhci_poll_and_HandleEvent(struct usb_device *usbdev) +{ + unsigned long ts; + struct xhci_ctrl *ctrl = usbdev->controller; + int event_occured = 0; + union xhci_trb *event; + union xhci_trb *first_trb; + + xhci_flush_inval_cache((uint32_t)ctrl->event_ring->dequeue, + XHCI_TRB, 0); + + event = ctrl->event_ring->dequeue; + + ts = get_timer(0); + + do { + if (xhci_poll(ctrl)) { + debug("Poll success\n"); + event_occured = 1; + break; + } + } while (get_timer(ts) < USB_CTRL_SET_TIMEOUT); + + if (event_occured) { + while (((le32_to_cpu(event->event_cmd.flags) & + TRB_TYPE_BITMASK) >> + TRB_TYPE_SHIFT) == TRB_PORT_STATUS) { + if (xhci_handle_event(ctrl) < 0) { + debug("Error in handling the event\n"); + return; + } + + first_trb = ctrl->event_ring->first_seg->trbs; + + xhci_flush_inval_cache((uint32_t)first_trb, + (sizeof(union xhci_trb) * 64), 0); + + event = ctrl->event_ring->dequeue; + } + /* + * If this is the 1st time POLL is called + * then handle event one more time, since + * 1st event would be "PORT STATUS CHANGE EVENT" + */ + if (xhci_handle_event(ctrl) < 0) { + debug("Error in handling the event\n"); + return; + } + usbdev->act_len = 0; + usbdev->status = 0; + } else { + debug("NO EVENT OCCURED\n"); + } + + return; +} + +/** + * Issue an Address Device command (which will issue a SetAddress request to + * the device). + * We add one to the device address issued by the hardware because the USB core + * uses address 1 for the root hubs (even though they're not really devices). + * + * @param usbdev pointer to the Device Data Structure + * @return 0 if successful else error code on failure + */ +int xhci_address_device(struct usb_device *usbdev) +{ + int ret = 0; + struct xhci_ctrl *ctrl = usbdev->controller; + struct xhci_slot_ctx *slot_ctx; + struct xhci_input_control_ctx *ctrl_ctx; + struct xhci_virt_device *virt_dev; + int slot_id = ctrl->slot_id; + + virt_dev = ctrl->devs[slot_id]; + + slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx); + + /* + * If this is the first Set Address since device plug-in or + * virt_device realloaction after a resume with an xHCI power loss, + * then set up the slot context. + */ + + xhci_flush_inval_cache((uint32_t)virt_dev->eps[0].ring->first_seg->trbs, + XHCI_TRB, 0); + xhci_flush_inval_cache((uint32_t)virt_dev->in_ctx, + XHCI_CTX, 0); + xhci_flush_inval_cache((uint32_t)virt_dev->out_ctx, + XHCI_CTX, 0); + xhci_flush_inval_cache((uint32_t)virt_dev->in_ctx->bytes, + virt_dev->in_ctx->size, 0); + xhci_flush_inval_cache((uint32_t)virt_dev->out_ctx->bytes, + virt_dev->out_ctx->size, 0); + + if (!slot_ctx->dev_info) { + debug("Setting up addressable devices\n"); + xhci_setup_addressable_virt_dev(usbdev); + } else { + /* Otherwise, update the control EP ring enqueue pointer. */ + debug("update the control endpoint ring enqueue pointer\n"); + xhci_copy_ep0_dequeue_into_input_ctx(ctrl); + } + + ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); + ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); + ctrl_ctx->drop_flags = 0; + + xhci_flush_inval_cache((uint32_t)virt_dev->in_ctx, + XHCI_CTX, 1); + xhci_flush_inval_cache((uint32_t)virt_dev->out_ctx, + XHCI_CTX, 1); + xhci_flush_inval_cache((uint32_t)virt_dev->in_ctx->bytes, + virt_dev->in_ctx->size, 1); + xhci_flush_inval_cache((uint32_t)virt_dev->out_ctx->bytes, + virt_dev->out_ctx->size, 1); + + ret = xhci_queue_address_device(ctrl, virt_dev->in_ctx->bytes, + slot_id); + + xhci_ring_cmd_db(ctrl); + mdelay(5); + xhci_poll_and_HandleEvent(usbdev); + + switch (virt_dev->cmd_status) { + case COMP_CTX_STATE: + case COMP_EBADSLT: + debug("Setup ERROR: address device command for slot %d.\n", + slot_id); + ret = -EINVAL; + break; + case COMP_TX_ERR: + debug("Device not responding to set address.\n"); + ret = -EPROTO; + break; + case COMP_DEV_ERR: + debug("ERROR: Incompatible device" + "for address device command.\n"); + ret = -ENODEV; + break; + case COMP_SUCCESS: + debug("Successful Address Device command\n"); + break; + default: + debug("ERROR: unexpected command completion code 0x%x.\n", + virt_dev->cmd_status); + /*FIXME*/ + ret = 0; + break; + } + if (ret < 0) + return ret; + /* + * USB core uses address 1 for the roothubs, so we add one to the + * address given back to us by the HC. + */ + + xhci_flush_inval_cache((uint32_t)virt_dev->out_ctx, + XHCI_CTX, 0); + xhci_flush_inval_cache((uint32_t)virt_dev->out_ctx->bytes, + virt_dev->out_ctx->size, 1); + + slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx); + + /* store xHC assigned Address locally */ + virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & + DEV_ADDR_MASK) + 1; + + if (virt_dev->address == 1) + debug("ADDRESS assigned is ZERO\n"); + + /* Zero the input context control for later use */ + ctrl_ctx->add_flags = 0; + ctrl_ctx->drop_flags = 0; + + return 0; +} + +/** + * Issue Enable slot command to the controller to allocate + * device slot and assign the slot id. It fails if the xHC + * ran out of device slots, the Enable Slot command timed out, + * or allocating memory failed. + * + * @param usbdev pointer to the Device Data Structure + * @return Returns 0 on succes else return -1 on failure + */ +int xhci_alloc_dev(struct usb_device *usbdev) +{ + struct xhci_ctrl *ctrl = usbdev->controller; + int ret; + ret = xhci_queue_slot_control(ctrl, TRB_ENABLE_SLOT, 0); + if (ret) { + debug("FIXME: allocate a command ring segment\n"); + return -1; + } + xhci_ring_cmd_db(ctrl); + mdelay(5); + xhci_poll_and_HandleEvent(usbdev); + if (!ctrl->slot_id) { + debug("Error while assigning device slot ID\n"); + return -1; + } + + /* + * Use GFP_NOIO, since this function can be called from + * xhci_discover_or_reset_device(), which may be called as part of + * mass storage driver error handling. + */ + if (xhci_alloc_virt_device(usbdev, ctrl->slot_id) < 0) + debug("Could not allocate xHCI USB device data structures\n"); + + return 0; +} + +/** + * Submits the INT request to XHCI Host cotroller + * + * @param usbdev pointer to the USB device + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @param interval interval of the interrupt + * @return 0 + */ +int +submit_int_msg(struct usb_device *usbdev, unsigned long pipe, void *buffer, + int length, int interval) +{ + /* Not addressing any interrupt type transfer requests */ + return 0; +} + +/** + * submit the BULK type of request to the USB Device + * + * @param usbdev pointer to the USB device + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @param length length of the buffer + * @return returns 0 if successful else -1 on failure + */ +int +submit_bulk_msg(struct usb_device *usbdev, unsigned long pipe, void *buffer, + int length) +{ + if (usb_pipetype(pipe) != PIPE_BULK) { + debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); + return -1; + } + return xhci_submit_async(usbdev, pipe, buffer, length, NULL); +} + +/** + * submit the control type of request to the Root hub/Device based on the devnum + * + * @param usbdev pointer to the USB device + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @param length length of the buffer + * @param setup Request type + * @return returns 0 if successful else -1 on failure + */ +int +submit_control_msg(struct usb_device *usbdev, unsigned long pipe, void *buffer, + int length, struct devrequest *setup) +{ + struct xhci_ctrl *ctrl = usbdev->controller; + int ret = -1; + + if (usb_pipetype(pipe) != PIPE_CONTROL) { + debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); + return -1; + } + if (setup->request == USB_REQ_SET_CONFIGURATION) { + if (usbdev->devnum > 1) { + xhci_submit_root(usbdev, pipe, buffer, length, setup); + return xhci_submit_async(usbdev, pipe, buffer, + length, setup); + } else { + usbdev->status = 0; + usbdev->act_len = length; + return 0; + } + } + + if (usb_pipedevice(pipe) == ctrl->rootdev) { + if (ctrl->rootdev == 0) + usbdev->speed = USB_SPEED_SUPER; + + return xhci_submit_root(usbdev, pipe, buffer, length, setup); + } + + if ((setup->request == USB_REQ_SET_ADDRESS)) + return xhci_submit_root(usbdev, pipe, buffer, length, setup); + + ret = xhci_submit_async(usbdev, pipe, buffer, length, setup); + + xhci_flush_inval_cache((uint32_t)buffer, length, 0); + + return ret; +} + +/** + * Allocates the necessary data structures + * for XHCI host controller + * + * @param index index to the host controller data structure + * @param hccr pointer HOST Controller Control Registers + * @param hcor pointer HOST Controller Operational Registers + * @return 0 if successful else -1 on failure + */ +int xhci_mem_init(int index, struct xhci_hccr *hccr, struct xhci_hcor *hcor) +{ + uint64_t val_64; + uint64_t trb_64; + uint32_t val; + uint32_t temp; + unsigned long deq; + int i; + struct xhci_segment *seg; + struct xhci_ctrl *ctrl = &xhcic[index]; + + /* DCBAA initialization */ + ctrl->dcbaa = (struct xhci_device_context_array *) + xhci_malloc(sizeof(struct xhci_device_context_array)); + if (ctrl->dcbaa == NULL) { + debug("unable to allocate DCBA\n"); + return -1; + } + + val_64 = (uintptr_t)ctrl->dcbaa; + /* Set the pointer in DCBAA register */ + xhci_writel_64(&hcor->or_dcbaap, val_64); + + /* Command ring control pointer register initialization */ + ctrl->cmd_ring = xhci_ring_alloc(1, true); + if (ctrl->cmd_ring == NULL) { + debug("unable to allocate TRB RING\n"); + free(ctrl->dcbaa); + return -1; + } + + /* Set the address in the Command Ring Control register */ + trb_64 = (uintptr_t)ctrl->cmd_ring->first_seg->trbs; + val_64 = xhci_readl_64(&hcor->or_crcr); + val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | + (trb_64 & (u64) ~CMD_RING_RSVD_BITS) | + ctrl->cmd_ring->cycle_state; + xhci_writel_64(&hcor->or_crcr, val_64); + + /* write the addres of db register */ + val = xhci_readl(&hccr->cr_dboff); + val &= DBOFF_MASK; + ctrl->dba = (struct xhci_doorbell_array *)((char *)hccr + val); + + /* write the addres of runtime register */ + val = xhci_readl(&hccr->cr_rtsoff); + val &= RTSOFF_MASK; + ctrl->run_regs = (struct xhci_run_regs *)((char *)hccr + val); + + /* writting the addrwess of ir_set structure */ + ctrl->ir_set = &ctrl->run_regs->ir_set[0]; + + /* Event ring does not maintain link TRB */ + ctrl->event_ring = xhci_ring_alloc(ERST_NUM_SEGS, false); + ctrl->erst.entries = (struct xhci_erst_entry *) + xhci_malloc(sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS); + + ctrl->erst.num_entries = ERST_NUM_SEGS; + + for (val = 0, seg = ctrl->event_ring->first_seg; + val < ERST_NUM_SEGS; + val++) { + trb_64 = 0; + trb_64 = (uintptr_t)seg->trbs; + struct xhci_erst_entry *entry = &ctrl->erst.entries[val]; + xhci_writel_64(&entry->seg_addr, trb_64); + entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); + entry->rsvd = 0; + seg = seg->next; + xhci_flush_inval_cache((uint32_t)entry, + sizeof(struct xhci_erst_entry), 1); + + } + + deq = (unsigned long)ctrl->event_ring->dequeue; + + xhci_flush_inval_cache((uint32_t)deq, XHCI_TRB, 1); + + /* Update HC event ring dequeue pointer */ + temp = xhci_readl_64(&ctrl->ir_set->erst_dequeue); + temp &= ERST_PTR_MASK; + + /* + * Don't clear the EHB bit (which is RW1C) because + * there might be more events to service. + */ + /* clearing the EHB bit here prior to writting the ERST dequeue */ + temp &= ~ERST_EHB; + xhci_writel_64(&ctrl->ir_set->erst_dequeue, + (((u64) deq & (u64) ~ERST_PTR_MASK) | temp)); + + /* set ERST count with the number of entries in the segment table */ + val = xhci_readl(&ctrl->ir_set->erst_size); + val &= ERST_SIZE_MASK; + val |= ERST_NUM_SEGS; + xhci_writel(&ctrl->ir_set->erst_size, val); + + /* this is the evenet ring segment table pointer */ + val_64 = xhci_readl_64(&ctrl->ir_set->erst_base); + val_64 &= ERST_PTR_MASK; + val_64 |= ((u32)(ctrl->erst.entries) & ~ERST_PTR_MASK); + + xhci_writel_64(&ctrl->ir_set->erst_base, val_64); + + /* initializing the viretualdevices to NULL */ + for (i = 0; i < MAX_HC_SLOTS; ++i) + ctrl->devs[i] = NULL; + + return 0; +} + +/** + * Intialises the XHCI host controller + * and allocates the necessary data structures + * + * @param index index to the host controller data structure + * @return pointer to the intialised controller + */ +int usb_lowlevel_init(int index, void **controller) +{ + uint32_t val; + uint32_t val2; + uint32_t temp; + uint32_t reg; + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + struct xhci_ctrl *ctrl; + + if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0) + return -ENODEV; + + if (xhci_halt(hcor) != 0) + return -ENODEV; + + if (xhci_reset(hcor) != 0) + return -ENODEV; + + ctrl = &xhcic[index]; + + ctrl->hccr = hccr; + ctrl->hcor = hcor; + + /* + * Program the Number of Device Slots Enabled field in the CONFIG + * register with the max value of slots the HC can handle. + */ + val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK); + val2 = xhci_readl(&hcor->or_config); + val |= (val2 & ~HCS_SLOTS_MASK); + xhci_writel(&hcor->or_config, val); + + /* initializing xhci data structures */ + if (xhci_mem_init(index, hccr, hcor) < 0) + return -ENOMEM; + + temp = xhci_readl(&hcor->or_dnctrl); + temp &= ~DEV_NOTE_MASK; + temp |= DEV_NOTE_FWAKE; + xhci_writel(&hcor->or_dnctrl, temp); + + reg = xhci_readl(&hccr->cr_hcsparams1); + descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >> + HCS_MAX_PORTS_SHIFT); + printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); + /* Port Indicators */ + if (HCS_INDICATOR(reg)) + descriptor.hub.wHubCharacteristics |= 0x80; + /* Port Power Control */ + if (HCC_PPC(reg)) + descriptor.hub.wHubCharacteristics |= 0x01; + else + descriptor.hub.wHubCharacteristics |= 0x02; + + /* per port overcurrent reporting */ + descriptor.hub.wHubCharacteristics |= 0x08; + + if (xhci_start(hcor)) { + xhci_halt(hcor); + return -ENODEV; + } + + temp = xhci_readl(&ctrl->ir_set->irq_control); + temp &= ~ER_IRQ_INTERVAL_MASK; + temp |= (u32) 160; + xhci_writel(&ctrl->ir_set->irq_control, temp); + + /* Set the HCD state before we enable the irqs */ + temp = xhci_readl(&hcor->or_usbcmd); + temp |= (CMD_EIE); + xhci_writel(&hcor->or_usbcmd, temp); + + temp = xhci_readl(&ctrl->ir_set->irq_pending); + xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_ENABLE(temp)); + + reg = HC_VERSION(xhci_readl(&hccr->cr_capbase)); + printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff); + + ctrl->rootdev = 0; + + *controller = &xhcic[index]; + return 0; +} + +/** + * Stops the XHCI host controller + * and cleans up all the related data structures + * + * @param index index to the host controller data structure + * @return none + */ +int usb_lowlevel_stop(int index) +{ + struct xhci_ctrl *ctrl = (xhcic + index); + + xhci_halt(ctrl->hcor); + xhci_reset(ctrl->hcor); + + xhci_hcd_stop(index); + + xhci_cleanup(ctrl); + + return 0; +} diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h new file mode 100644 index 0000000..f1a583b --- /dev/null +++ b/drivers/usb/host/xhci.h @@ -0,0 +1,1360 @@ +/* + * USB HOST XHCI Controller + * + * Copyright (C) 2012 Samsung Electronics Co.Ltd + * Vivek Gautam gautam.vivek@samsung.com + * Vikas Sajjan vikas.sajjan@samsung.com + * + * Based on xHCI host controller driver in linux-kernel + * by Sarah Sharp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef HOST_XHCI_H_ +#define HOST_XHCI_H_ + +#include <asm/cache.h> +#include <linux/list.h> + +typedef enum { false = 0, true = 1 } bool; + +/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */ +#define DeviceRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) + +#define DeviceOutRequest \ + ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) + +#define InterfaceRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +#define EndpointRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +#define EndpointOutRequest \ + ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +#define upper_32_bits(n) (u32)(((n) >> 32) & 0xffffffff) +#define lower_32_bits(n) (u32)(n) + +#define MAX_EP_CTX_NUM 31 +#define USB_CTRL_SET_TIMEOUT 5000 +#define XHCI_ALIGNMENT 64 +/* Max number of USB devices for any host controller - limit in section 6.1 */ +#define MAX_HC_SLOTS 256 +/* Section 5.3.3 - MaxPorts */ +#define MAX_HC_PORTS 127 + +/* Up to 16 ms to halt an HC */ +#define XHCI_MAX_HALT_USEC (16*1000) + +#define XHCI_MAX_RESET_USEC (250*1000) + +/* + * These bits are Read Only (RO) and should be saved and written to the + * registers: 0, 3, 10:13, 30 + * connect status, over-current status, port speed, and device removable. + * connect status and port speed are also sticky - meaning they're in + * the AUX well and they aren't changed by a hot, warm, or cold reset. + */ +#define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30)) +/* + * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: + * bits 5:8, 9, 14:15, 25:27 + * link state, port power, port indicator state, "wake on" enable state + */ +#define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25)) +/* + * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: + * bit 4 (port reset) + */ +#define XHCI_PORT_RW1S ((1 << 4)) +/* + * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: + * bits 1, 17, 18, 19, 20, 21, 22, 23 + * port enable/disable, and + * change bits: connect, PED, + * warm port reset changed (reserved zero for USB 2.0 ports), + * over-current, reset, link state, and L1 change + */ +#define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17)) +/* + * Bit 16 is RW, and writing a '1' to it causes the link state control to be + * latched in + */ +#define XHCI_PORT_RW ((1 << 16)) +/* + * These bits are Reserved Zero (RsvdZ) and zero should be written to them: + * bits 2, 24, 28:31 + */ +#define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28)) + +/* + * XHCI Register Space. + */ +struct xhci_hccr { + uint32_t cr_capbase; + uint32_t cr_hcsparams1; + uint32_t cr_hcsparams2; + uint32_t cr_hcsparams3; + uint32_t cr_hccparams; + uint32_t cr_dboff; + uint32_t cr_rtsoff; + +/* hc_capbase bitmasks */ +/* bits 7:0 - how long is the Capabilities register */ +#define HC_LENGTH(p) XHCI_HC_LENGTH(p) +/* bits 31:16 */ +#define HC_VERSION(p) (((p) >> 16) & 0xffff) + +/* HCSPARAMS1 - hcs_params1 - bitmasks */ +/* bits 0:7, Max Device Slots */ +#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) +#define HCS_SLOTS_MASK 0xff +/* bits 8:18, Max Interrupters */ +#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) +/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ +#define HCS_MAX_PORTS_SHIFT 24 +#define HCS_MAX_PORTS_MASK (0x7f << HCS_MAX_PORTS_SHIFT) +#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) + +/* HCSPARAMS2 - hcs_params2 - bitmasks */ +/* bits 0:3, frames or uframes that SW needs to queue transactions + * ahead of the HW to meet periodic deadlines */ +#define HCS_IST(p) (((p) >> 0) & 0xf) +/* bits 4:7, max number of Event Ring segments */ +#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) +/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ +/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ +#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) + +/* HCSPARAMS3 - hcs_params3 - bitmasks */ +/* bits 0:7, Max U1 to U0 latency for the roothub ports */ +#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) +/* bits 16:31, Max U2 to U0 latency for the roothub ports */ +#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) + +/* HCCPARAMS - hcc_params - bitmasks */ +/* true: HC can use 64-bit address pointers */ +#define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) +/* true: HC can do bandwidth negotiation */ +#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) +/* true: HC uses 64-byte Device Context structures + * FIXME 64-byte context structures aren't supported yet. + */ +#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) +/* true: HC has port power switches */ +#define HCC_PPC(p) ((p) & (1 << 3)) +/* true: HC has port indicators */ +#define HCS_INDICATOR(p) ((p) & (1 << 4)) +/* true: HC has Light HC Reset Capability */ +#define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) +/* true: HC supports latency tolerance messaging */ +#define HCC_LTC(p) ((p) & (1 << 6)) +/* true: no secondary Stream ID Support */ +#define HCC_NSS(p) ((p) & (1 << 7)) +/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ +#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) +/* Extended Capabilities pointer from PCI base - section 5.3.6 */ +#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) + +/* db_off bitmask - bits 0:1 reserved */ +#define DBOFF_MASK (~0x3) + +/* run_regs_off bitmask - bits 0:4 reserved */ +#define RTSOFF_MASK (~0x1f) + +}; + +struct xhci_hcor_portRegss { + volatile uint32_t or_portsc; + volatile uint32_t or_portpmsc; + volatile uint32_t or_portli; + volatile uint32_t reserved_3; +}; + +struct xhci_hcor { + volatile uint32_t or_usbcmd; + volatile uint32_t or_usbsts; + volatile uint32_t or_pagesize; + volatile uint32_t reserved_0[2]; + volatile uint32_t or_dnctrl; + volatile uint64_t or_crcr; + volatile uint32_t reserved_1[4]; + volatile uint64_t or_dcbaap; + volatile uint32_t or_config; + volatile uint32_t reserved_2[241]; + struct xhci_hcor_portRegss PortRegs[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS]; + + uint32_t reserved_4[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS*254]; +}; + +/* USBCMD - USB command - command bitmasks */ +/* start/stop HC execution - do not write unless HC is halted*/ +#define CMD_RUN XHCI_CMD_RUN +/* Reset HC - resets internal HC state machine and all registers (except + * PCI config regs). HC does NOT drive a USB reset on the downstream ports. + * The xHCI driver must reinitialize the xHC after setting this bit. + */ +#define CMD_RESET (1 << 1) +/* Event Interrupt Enable - a '1' allows interrupts from the host controller */ +#define CMD_EIE XHCI_CMD_EIE +/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ +#define CMD_HSEIE XHCI_CMD_HSEIE +/* bits 4:6 are reserved (and should be preserved on writes). */ +/* light reset (port status stays unchanged) - reset completed when this is 0 */ +#define CMD_LRESET (1 << 7) +/* host controller save/restore state. */ +#define CMD_CSS (1 << 8) +#define CMD_CRS (1 << 9) +/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ +#define CMD_EWE XHCI_CMD_EWE +/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root + * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. + * '0' means the xHC can power it off if all ports are in the disconnect, + * disabled, or powered-off state. + */ +#define CMD_PM_INDEX (1 << 11) +/* bits 12:31 are reserved (and should be preserved on writes). */ + +/* USBSTS - USB status - status bitmasks */ +/* HC not running - set to 1 when run/stop bit is cleared. */ +#define STS_HALT XHCI_STS_HALT +/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ +#define STS_FATAL (1 << 2) +/* event interrupt - clear this prior to clearing any IP flags in IR set*/ +#define STS_EINT (1 << 3) +/* port change detect */ +#define STS_PORT (1 << 4) +/* bits 5:7 reserved and zeroed */ +/* save state status - '1' means xHC is saving state */ +#define STS_SAVE (1 << 8) +/* restore state status - '1' means xHC is restoring state */ +#define STS_RESTORE (1 << 9) +/* true: save or restore error */ +#define STS_SRE (1 << 10) +/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ +#define STS_CNR XHCI_STS_CNR +/* true: internal Host Controller Error - SW needs to reset and reinitialize */ +#define STS_HCE (1 << 12) +/* bits 13:31 reserved and should be preserved */ + +/* + * DNCTRL - Device Notification Control Register - dev_notification bitmasks + * Generate a device notification event when the HC sees a transaction with a + * notification type that matches a bit set in this bit field. + */ +#define DEV_NOTE_MASK (0xffff) +#define ENABLE_DEV_NOTE(x) (1 << (x)) +/* Most of the device notification types should only be used for debug. + * SW does need to pay attention to function wake notifications. + */ +#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) + +/* CRCR - Command Ring Control Register - cmd_ring bitmasks */ +/* bit 0 is the command ring cycle state */ +/* stop ring operation after completion of the currently executing command */ +#define CMD_RING_PAUSE (1 << 1) +/* stop ring immediately - abort the currently executing command */ +#define CMD_RING_ABORT (1 << 2) +/* true: command ring is running */ +#define CMD_RING_RUNNING (1 << 3) +/* bits 4:5 reserved and should be preserved */ +/* Command Ring pointer - bit mask for the lower 32 bits. */ +#define CMD_RING_RSVD_BITS (0x3f) + +/* CONFIG - Configure Register - config_reg bitmasks */ +/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ +#define MAX_DEVS(p) ((p) & 0xff) +/* bits 8:31 - reserved and should be preserved */ + +/* PORTSC - Port Status and Control Register - port_status_base bitmasks */ +/* true: device connected */ +#define PORT_CONNECT (1 << 0) +/* true: port enabled */ +#define PORT_PE (1 << 1) +/* bit 2 reserved and zeroed */ +/* true: port has an over-current condition */ +#define PORT_OC (1 << 3) +/* true: port reset signaling asserted */ +#define PORT_RESET (1 << 4) +/* Port Link State - bits 5:8 + * A read gives the current link PM state of the port, + * a write with Link State Write Strobe set sets the link state. + */ +#define PORT_PLS_MASK (0xf << 5) +#define XDEV_U0 (0x0 << 5) +#define XDEV_U2 (0x2 << 5) +#define XDEV_U3 (0x3 << 5) +#define XDEV_RESUME (0xf << 5) +/* true: port has power (see HCC_PPC) */ +#define PORT_POWER (1 << 9) +/* bits 10:13 indicate device speed: + * 0 - undefined speed - port hasn't be initialized by a reset yet + * 1 - full speed + * 2 - low speed + * 3 - high speed + * 4 - super speed + * 5-15 reserved + */ +#define DEV_SPEED_MASK (0xf << 10) +#define XDEV_FS (0x1 << 10) +#define XDEV_LS (0x2 << 10) +#define XDEV_HS (0x3 << 10) +#define XDEV_SS (0x4 << 10) +#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) +#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) +#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) +#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) +#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) +/* Bits 20:23 in the Slot Context are the speed for the device */ +#define SLOT_SPEED_FS (XDEV_FS << 10) +#define SLOT_SPEED_LS (XDEV_LS << 10) +#define SLOT_SPEED_HS (XDEV_HS << 10) +#define SLOT_SPEED_SS (XDEV_SS << 10) +/* Port Indicator Control */ +#define PORT_LED_OFF (0 << 14) +#define PORT_LED_AMBER (1 << 14) +#define PORT_LED_GREEN (2 << 14) +#define PORT_LED_MASK (3 << 14) +/* Port Link State Write Strobe - set this when changing link state */ +#define PORT_LINK_STROBE (1 << 16) +/* true: connect status change */ +#define PORT_CSC (1 << 17) +/* true: port enable change */ +#define PORT_PEC (1 << 18) +/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port + * into an enabled state, and the device into the default state. A "warm" reset + * also resets the link, forcing the device through the link training sequence. + * SW can also look at the Port Reset register to see when warm reset is done. + */ +#define PORT_WRC (1 << 19) +/* true: over-current change */ +#define PORT_OCC (1 << 20) +/* true: reset change - 1 to 0 transition of PORT_RESET */ +#define PORT_RC (1 << 21) +/* port link status change - set on some port link state transitions: + * Transition Reason + * -------------------------------------------------------------------------- + * - U3 to Resume Wakeup signaling from a device + * - Resume to Recovery to U0 USB 3.0 device resume + * - Resume to U0 USB 2.0 device resume + * - U3 to Recovery to U0 Software resume of USB 3.0 device complete + * - U3 to U0 Software resume of USB 2.0 device complete + * - U2 to U0 L1 resume of USB 2.1 device complete + * - U0 to U0 (???) L1 entry rejection by USB 2.1 device + * - U0 to disabled L1 entry error with USB 2.1 device + * - Any state to inactive Error on USB 3.0 port + */ +#define PORT_PLC (1 << 22) +/* port configure error change - port failed to configure its link partner */ +#define PORT_CEC (1 << 23) +/* bit 24 reserved */ +/* wake on connect (enable) */ +#define PORT_WKCONN_E (1 << 25) +/* wake on disconnect (enable) */ +#define PORT_WKDISC_E (1 << 26) +/* wake on over-current (enable) */ +#define PORT_WKOC_E (1 << 27) +/* bits 28:29 reserved */ +/* true: device is removable - for USB 3.0 roothub emulation */ +#define PORT_DEV_REMOVE (1 << 30) +/* Initiate a warm port reset - complete when PORT_WRC is '1' */ +#define PORT_WR (1 << 31) + +/* We mark duplicate entries with -1 */ +#define DUPLICATE_ENTRY ((u8)(-1)) + +/* Port Power Management Status and Control - port_power_base bitmasks */ +/* Inactivity timer value for transitions into U1, in microseconds. + * Timeout can be up to 127us. 0xFF means an infinite timeout. + */ +#define PORT_U1_TIMEOUT(p) ((p) & 0xff) +/* Inactivity timer value for transitions into U2 */ +#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) +/* Bits 24:31 for port testing */ + +/* USB2 Protocol PORTSPMSC */ +#define PORT_L1S_MASK 7 +#define PORT_L1S_SUCCESS 1 +#define PORT_RWE (1 << 3) +#define PORT_HIRD(p) (((p) & 0xf) << 4) +#define PORT_HIRD_MASK (0xf << 4) +#define PORT_L1DS(p) (((p) & 0xff) << 8) +#define PORT_HLE (1 << 16) + +#define USBMODE 0x68 /* USB Device mode */ +#define USBMODE_SDIS (1 << 3) /* Stream disable */ +#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */ +#define USBMODE_CM_HC (3 << 0) /* host controller mode */ +#define USBMODE_CM_IDLE (0 << 0) /* idle state */ + +/** +* struct xhci_intr_reg - Interrupt Register Set +* @irq_pending: IMAN - Interrupt Management Register. Used to enable +* interrupts and check for pending interrupts. +* @irq_control: IMOD - Interrupt Moderation Register. +* Used to throttle interrupts. +* @erst_size: Number of segments in the + Event Ring Segment Table (ERST). +* @erst_base: ERST base address. +* @erst_dequeue: Event ring dequeue pointer. +* +* Each interrupter (defined by a MSI-X vector) has an event ring and an Event +* Ring Segment Table (ERST) associated with it. +* The event ring is comprised of multiple segments of the same size. +* The HC places events on the ring and "updates the Cycle bit in the TRBs to +* indicate to software the current position of the Enqueue Pointer." +* The HCD (Linux) processes those events and updates the dequeue pointer. +*/ +struct xhci_intr_reg { + volatile __le32 irq_pending; + volatile __le32 irq_control; + volatile __le32 erst_size; + volatile __le32 rsvd; + volatile __le64 erst_base; + volatile __le64 erst_dequeue; +}; + +/* irq_pending bitmasks */ +#define ER_IRQ_PENDING(p) ((p) & 0x1) +/* bits 2:31 need to be preserved */ +/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ +#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) +#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) +#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) + +/* irq_control bitmasks */ +/* Minimum interval between interrupts (in 250ns intervals). The interval + * between interrupts will be longer if there are no events on the event ring. + * Default is 4000 (1 ms). + */ +#define ER_IRQ_INTERVAL_MASK (0xffff) +/* Counter used to count down the time to the next interrupt - HW use only */ +#define ER_IRQ_COUNTER_MASK (0xffff << 16) + +/* erst_size bitmasks */ +/* Preserve bits 16:31 of erst_size */ +#define ERST_SIZE_MASK (0xffff << 16) + +/* erst_dequeue bitmasks */ +/* Dequeue ERST Segment Index (DESI) - Segment number (or alias) + * where the current dequeue pointer lies. This is an optional HW hint. + */ +#define ERST_DESI_MASK (0x7) +/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by + * a work queue (or delayed service routine)? + */ +#define ERST_EHB (1 << 3) +#define ERST_PTR_MASK (0xf) + +/** + * struct xhci_run_regs + * @microframe_index: MFINDEX - current microframe number + * + * Section 5.5 Host Controller Runtime Registers: + * "Software should read and write these registers using only Dword (32 bit) + * or larger accesses" + */ +struct xhci_run_regs { + __le32 microframe_index; + __le32 rsvd[7]; + struct xhci_intr_reg ir_set[128]; +}; + +/** + * struct doorbell_array + * + * Bits 0 - 7: Endpoint target + * Bits 8 - 15: RsvdZ + * Bits 16 - 31: Stream ID + * + * Section 5.6 + */ +struct xhci_doorbell_array { + volatile __le32 doorbell[256]; +}; + +#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) +#define DB_VALUE_HOST 0x00000000 + +/** + * struct xhci_protocol_caps + * @revision: major revision, minor revision, capability ID, + * and next capability pointer. + * @name_string: Four ASCII characters to say which spec this xHC + * follows, typically "USB ". + * @port_info: Port offset, count, and protocol-defined information. + */ +struct xhci_protocol_caps { + u32 revision; + u32 name_string; + u32 port_info; +}; + +#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) +#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) +#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) + +/** + * struct xhci_container_ctx + * @type: Type of context. Used to calculated offsets to contained contexts. + * @size: Size of the context data + * @bytes: The raw context data given to HW + * @dma: dma address of the bytes + * + * Represents either a Device or Input context. Holds a pointer to the raw + * memory used for the context (bytes) and dma address of it (dma). + */ +struct xhci_container_ctx { + unsigned type; +#define XHCI_CTX_TYPE_DEVICE 0x1 +#define XHCI_CTX_TYPE_INPUT 0x2 + + int size; + u8 *bytes; +}; + +/** + * struct xhci_slot_ctx + * @dev_info: Route string, device speed, hub info, and last valid endpoint + * @dev_info2: Max exit latency for device number, root hub port number + * @tt_info: tt_info is used to construct split transaction tokens + * @dev_state: slot state and device address + * + * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context + * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes + * reserved at the end of the slot context for HC internal use. + */ +struct xhci_slot_ctx { + __le32 dev_info; + __le32 dev_info2; + __le32 tt_info; + __le32 dev_state; + /* offset 0x10 to 0x1f reserved for HC internal use */ + __le32 reserved[4]; +}; + +/* dev_info bitmasks */ +/* Route String - 0:19 */ +#define ROUTE_STRING_MASK (0xfffff) +/* Device speed - values defined by PORTSC Device Speed field - 20:23 */ +#define DEV_SPEED (0xf << 20) +/* bit 24 reserved */ +/* Is this LS/FS device connected through a HS hub? - bit 25 */ +#define DEV_MTT (0x1 << 25) +/* Set if the device is a hub - bit 26 */ +#define DEV_HUB (0x1 << 26) +/* Index of the last valid endpoint context in this device context - 27:31 */ +#define LAST_CTX_MASK (0x1f << 27) +#define LAST_CTX(p) ((p) << 27) +#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) +#define SLOT_FLAG (1 << 0) +#define EP0_FLAG (1 << 1) + +/* dev_info2 bitmasks */ +/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ +#define MAX_EXIT (0xffff) +/* Root hub port number that is needed to access the USB device */ +#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) +#define ROOT_HUB_PORT_MASK (0xff) +#define ROOT_HUB_PORT_SHIFT (16) +#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) +/* Maximum number of ports under a hub device */ +#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) + +/* tt_info bitmasks */ +/* + * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub + * The Slot ID of the hub that isolates the high speed signaling from + * this low or full-speed device. '0' if attached to root hub port. + */ +#define TT_SLOT (0xff) +/* + * The number of the downstream facing port of the high-speed hub + * '0' if the device is not low or full speed. + */ +#define TT_PORT (0xff << 8) +#define TT_THINK_TIME(p) (((p) & 0x3) << 16) + +/* dev_state bitmasks */ +/* USB device address - assigned by the HC */ +#define DEV_ADDR_MASK (0xff) +/* bits 8:26 reserved */ +/* Slot state */ +#define SLOT_STATE (0x1f << 27) +#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) + +#define SLOT_STATE_DISABLED 0 +#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED +#define SLOT_STATE_DEFAULT 1 +#define SLOT_STATE_ADDRESSED 2 +#define SLOT_STATE_CONFIGURED 3 + +/** + * struct xhci_ep_ctx + * @ep_info: endpoint state, streams, mult, and interval information. + * @ep_info2: information on endpoint type, max packet size, max burst size, + * error count, and whether the HC will force an event for all + * transactions. + * @deq: 64-bit ring dequeue pointer address. If the endpoint only + * defines one stream, this points to the endpoint transfer ring. + * Otherwise, it points to a stream context array, which has a + * ring pointer for each flow. + * @tx_info: + * Average TRB lengths for the endpoint ring and + * max payload within an Endpoint Service Interval Time (ESIT). + * + * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context + * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes + * reserved at the end of the endpoint context for HC internal use. + */ +struct xhci_ep_ctx { + __le32 ep_info; + __le32 ep_info2; + __le64 deq; + __le32 tx_info; + /* offset 0x14 - 0x1f reserved for HC internal use */ + __le32 reserved[3]; +}; + +/* ep_info bitmasks */ +/* + * Endpoint State - bits 0:2 + * 0 - disabled + * 1 - running + * 2 - halted due to halt condition - ok to manipulate endpoint ring + * 3 - stopped + * 4 - TRB error + * 5-7 - reserved + */ +#define EP_STATE_MASK (0xf) +#define EP_STATE_DISABLED 0 +#define EP_STATE_RUNNING 1 +#define EP_STATE_HALTED 2 +#define EP_STATE_STOPPED 3 +#define EP_STATE_ERROR 4 +/* Mult - Max number of burtst within an interval, in EP companion desc. */ +#define EP_MULT(p) (((p) & 0x3) << 8) +#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) +/* bits 10:14 are Max Primary Streams */ +/* bit 15 is Linear Stream Array */ +/* Interval - period between requests to an endpoint - 125u increments. */ +#define EP_INTERVAL(p) (((p) & 0xff) << 16) +#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) +#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) +#define EP_MAXPSTREAMS_MASK (0x1f << 10) +#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) +/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ +#define EP_HAS_LSA (1 << 15) + +/* ep_info2 bitmasks */ +/* + * Force Event - generate transfer events for all TRBs for this endpoint + * This will tell the HC to ignore the IOC and ISP flags (for debugging only). + */ +#define FORCE_EVENT (0x1) +#define ERROR_COUNT(p) (((p) & 0x3) << 1) +#define ERROR_COUNT_SHIFT (1) +#define ERROR_COUNT_MASK (0x3) +#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) +#define EP_TYPE(p) ((p) << 3) +#define EP_TYPE_SHIFT (3) +#define ISOC_OUT_EP 1 +#define BULK_OUT_EP 2 +#define INT_OUT_EP 3 +#define CTRL_EP 4 +#define ISOC_IN_EP 5 +#define BULK_IN_EP 6 +#define INT_IN_EP 7 +/* bit 6 reserved */ +/* bit 7 is Host Initiate Disable - for disabling stream selection */ +#define MAX_BURST(p) (((p)&0xff) << 8) +#define MAX_BURST_MASK (0xff) +#define MAX_BURST_SHIFT (8) +#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) +#define MAX_PACKET(p) (((p)&0xffff) << 16) +#define MAX_PACKET_MASK (0xffff) +#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) +#define MAX_PACKET_SHIFT (16) + +/* Get max packet size from ep desc. Bit 10..0 specify the max packet size. + * USB2.0 spec 9.6.6. + */ +#define GET_MAX_PACKET(p) ((p) & 0x7ff) + +/* tx_info bitmasks */ +#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) +#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) +#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) + +/* deq bitmasks */ +#define EP_CTX_CYCLE_MASK (1 << 0) + + +/** + * struct xhci_input_control_context + * Input control context; see section 6.2.5. + * + * @drop_context: set the bit of the endpoint context you want to disable + * @add_context: set the bit of the endpoint context you want to enable + */ +struct xhci_input_control_ctx { + volatile __le32 drop_flags; + volatile __le32 add_flags; + __le32 rsvd2[6]; +}; + + +/** + * struct xhci_device_context_array + * @dev_context_ptr array of 64-bit DMA addresses for device contexts + */ +struct xhci_device_context_array { + /* 64-bit device addresses; we only write 32-bit addresses */ + __le64 dev_context_ptrs[MAX_HC_SLOTS]; +}; +/* TODO: write function to set the 64-bit device DMA address */ +/* + * TODO: change this to be dynamically sized at HC mem init time since the HC + * might not be able to handle the maximum number of devices possible. + */ + + +struct xhci_transfer_event { + /* 64-bit buffer address, or immediate data */ + __le64 buffer; + __le32 transfer_len; + /* This field is interpreted differently based on the type of TRB */ + volatile __le32 flags; +}; + +/** Transfer Event bit fields **/ +#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) + +/* Completion Code - only applicable for some types of TRBs */ +#define COMP_CODE_MASK (0xff << 24) +#define COMP_CODE_SHIFT (24) +#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) + +typedef enum { + COMP_SUCCESS = 1, + /* Data Buffer Error */ + COMP_DB_ERR, /* 2 */ + /* Babble Detected Error */ + COMP_BABBLE, /* 3 */ + /* USB Transaction Error */ + COMP_TX_ERR, /* 4 */ + /* TRB Error - some TRB field is invalid */ + COMP_TRB_ERR, /* 5 */ + /* Stall Error - USB device is stalled */ + COMP_STALL, /* 6 */ + /* Resource Error - HC doesn't have memory for that device configuration */ + COMP_ENOMEM, /* 7 */ + /* Bandwidth Error - not enough room in schedule for this dev config */ + COMP_BW_ERR, /* 8 */ + /* No Slots Available Error - HC ran out of device slots */ + COMP_ENOSLOTS, /* 9 */ + /* Invalid Stream Type Error */ + COMP_STREAM_ERR, /* 10 */ + /* Slot Not Enabled Error - doorbell rung for disabled device slot */ + COMP_EBADSLT, /* 11 */ + /* Endpoint Not Enabled Error */ + COMP_EBADEP,/* 12 */ + /* Short Packet */ + COMP_SHORT_TX, /* 13 */ + /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ + COMP_UNDERRUN, /* 14 */ + /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ + COMP_OVERRUN, /* 15 */ + /* Virtual Function Event Ring Full Error */ + COMP_VF_FULL, /* 16 */ + /* Parameter Error - Context parameter is invalid */ + COMP_EINVAL, /* 17 */ + /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ + COMP_BW_OVER,/* 18 */ + /* Context State Error - illegal context state transition requested */ + COMP_CTX_STATE,/* 19 */ + /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ + COMP_PING_ERR,/* 20 */ + /* Event Ring is full */ + COMP_ER_FULL,/* 21 */ + /* Incompatible Device Error */ + COMP_DEV_ERR,/* 22 */ + /* Missed Service Error - HC couldn't service an isoc ep within interval */ + COMP_MISSED_INT,/* 23 */ + /* Successfully stopped command ring */ + COMP_CMD_STOP, /* 24 */ + /* Successfully aborted current command and stopped command ring */ + COMP_CMD_ABORT, /* 25 */ + /* Stopped - transfer was terminated by a stop endpoint command */ + COMP_STOP,/* 26 */ + /* Same as COMP_EP_STOPPED, but the transferred length in the event + * is invalid */ + COMP_STOP_INVAL, /* 27*/ + /* Control Abort Error - Debug Capability - control pipe aborted */ + COMP_DBG_ABORT, /* 28 */ + /* Max Exit Latency Too Large Error */ + COMP_MEL_ERR,/* 29 */ + /* TRB type 30 reserved */ + /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ + COMP_BUFF_OVER = 31, + /* Event Lost Error - xHC has an "internal event overrun condition" */ + COMP_ISSUES, /* 32 */ + /* Undefined Error - reported when other error codes don't apply */ + COMP_UNKNOWN, /* 33 */ + /* Invalid Stream ID Error */ + COMP_STRID_ERR, /* 34 */ + /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ + COMP_2ND_BW_ERR, /* 35 */ + /* Split Transaction Error */ + COMP_SPLIT_ERR /* 36 */ + +} xhci_comp_code; + +struct xhci_link_trb { + /* 64-bit segment pointer*/ + volatile __le64 segment_ptr; + volatile __le32 intr_target; + volatile __le32 control; +}; + +/* control bitfields */ +#define LINK_TOGGLE (0x1 << 1) + +/* Command completion event TRB */ +struct xhci_event_cmd { + /* Pointer to command TRB, or the value passed by the event data trb */ + volatile __le64 cmd_trb; + volatile __le32 status; + volatile __le32 flags; +}; + +/* flags bitmasks */ +/* bits 16:23 are the virtual function ID */ +/* bits 24:31 are the slot ID */ +#define TRB_TO_SLOT_ID(p) (((p) & (0xff << 24)) >> 24) +#define TRB_TO_SLOT_ID_SHIFT (24) +#define TRB_TO_SLOT_ID_MASK (0xff << TRB_TO_SLOT_ID_SHIFT) +#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) +#define SLOT_ID_FOR_TRB_MASK (0xff) +#define SLOT_ID_FOR_TRB_SHIFT (24) + +/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ +#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) +#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) + +#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) +#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) +#define LAST_EP_INDEX 30 + +/* Set TR Dequeue Pointer command TRB fields */ +#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) +#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) + + +/* Port Status Change Event TRB fields */ +/* Port ID - bits 31:24 */ +#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) +#define PORT_ID_SHIFT (24) +#define PORT_ID_MASK (0xff << PORT_ID_SHIFT) + +/* Normal TRB fields */ +/* transfer_len bitmasks - bits 0:16 */ +#define TRB_LEN(p) ((p) & 0x1ffff) +#define TRB_LEN_MASK (0x1ffff) +/* Interrupter Target - which MSI-X vector to target the completion event at */ +#define TRB_INTR_TARGET_SHIFT (22) +#define TRB_INTR_TARGET_MASK (0x3ff) +#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) +#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) +#define TRB_TBC(p) (((p) & 0x3) << 7) +#define TRB_TLBPC(p) (((p) & 0xf) << 16) + +/* Cycle bit - indicates TRB ownership by HC or HCD */ +#define TRB_CYCLE (1<<0) +/* + * Force next event data TRB to be evaluated before task switch. + * Used to pass OS data back after a TD completes. + */ +#define TRB_ENT (1<<1) +/* Interrupt on short packet */ +#define TRB_ISP (1<<2) +/* Set PCIe no snoop attribute */ +#define TRB_NO_SNOOP (1<<3) +/* Chain multiple TRBs into a TD */ +#define TRB_CHAIN (1<<4) +/* Interrupt on completion */ +#define TRB_IOC (1<<5) +/* The buffer pointer contains immediate data */ +#define TRB_IDT (1<<6) + +/* Block Event Interrupt */ +#define TRB_BEI (1<<9) + +/* Control transfer TRB specific fields */ +#define TRB_DIR_IN (1<<16) +#define TRB_TX_TYPE(p) ((p) << 16) +#define TRB_TX_TYPE_SHIFT (16) +#define TRB_DATA_OUT 2 +#define TRB_DATA_IN 3 + +/* Isochronous TRB specific fields */ +#define TRB_SIA (1 << 31) + +struct xhci_generic_trb { + volatile __le32 field[4]; +}; + +union xhci_trb { + struct xhci_link_trb link; + struct xhci_transfer_event trans_event; + struct xhci_event_cmd event_cmd; + struct xhci_generic_trb generic; +}; + +/* TRB bit mask */ +#define TRB_TYPE_BITMASK (0xfc00) +#define TRB_TYPE(p) ((p) << 10) +#define TRB_TYPE_SHIFT (10) +#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) + +/* TRB type IDs */ +typedef enum { + /* bulk, interrupt, isoc scatter/gather, and control data stage */ + TRB_NORMAL = 1, + /* setup stage for control transfers */ + TRB_SETUP, /* 2 */ + /* data stage for control transfers */ + TRB_DATA, /* 3 */ + /* status stage for control transfers */ + TRB_STATUS, /* 4 */ + /* isoc transfers */ + TRB_ISOC, /* 5 */ + /* TRB for linking ring segments */ + TRB_LINK, /* 6 */ + /* TRB for EVENT DATA */ + TRB_EVENT_DATA, /* 7 */ + /* Transfer Ring No-op (not for the command ring) */ + TRB_TR_NOOP, /* 8 */ + /* Command TRBs */ + /* Enable Slot Command */ + TRB_ENABLE_SLOT, /* 9 */ + /* Disable Slot Command */ + TRB_DISABLE_SLOT, /* 10 */ + /* Address Device Command */ + TRB_ADDR_DEV, /* 11 */ + /* Configure Endpoint Command */ + TRB_CONFIG_EP, /* 12 */ + /* Evaluate Context Command */ + TRB_EVAL_CONTEXT, /* 13 */ + /* Reset Endpoint Command */ + TRB_RESET_EP, /* 14 */ + /* Stop Transfer Ring Command */ + TRB_STOP_RING, /* 15 */ + /* Set Transfer Ring Dequeue Pointer Command */ + TRB_SET_DEQ, /* 16 */ + /* Reset Device Command */ + TRB_RESET_DEV, /* 17 */ + /* Force Event Command (opt) */ + TRB_FORCE_EVENT, /* 18 */ + /* Negotiate Bandwidth Command (opt) */ + TRB_NEG_BANDWIDTH, /* 19 */ + /* Set Latency Tolerance Value Command (opt) */ + TRB_SET_LT, /* 20 */ + /* Get port bandwidth Command */ + TRB_GET_BW, /* 21 */ + /* Force Header Command - generate a transaction or link management packet */ + TRB_FORCE_HEADER, /* 22 */ + /* No-op Command - not for transfer rings */ + TRB_CMD_NOOP, /* 23 */ + /* TRB IDs 24-31 reserved */ + /* Event TRBS */ + /* Transfer Event */ + TRB_TRANSFER = 32, + /* Command Completion Event */ + TRB_COMPLETION, /* 33 */ + /* Port Status Change Event */ + TRB_PORT_STATUS, /* 34 */ + /* Bandwidth Request Event (opt) */ + TRB_BANDWIDTH_EVENT, /* 35 */ + /* Doorbell Event (opt) */ + TRB_DOORBELL, /* 36 */ + /* Host Controller Event */ + TRB_HC_EVENT, /* 37 */ + /* Device Notification Event - device sent function wake notification */ + TRB_DEV_NOTE, /* 38 */ + /* MFINDEX Wrap Event - microframe counter wrapped */ + TRB_MFINDEX_WRAP, /* 39 */ + /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ + /* Nec vendor-specific command completion event. */ + TRB_NEC_CMD_COMP = 48, /* 48 */ + /* Get NEC firmware revision. */ + TRB_NEC_GET_FW, /* 49 */ +} trb_type; + +#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) +/* Above, but for __le32 types -- can avoid work by swapping constants: */ +#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ + cpu_to_le32(TRB_TYPE(TRB_LINK))) +#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ + cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) + +#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) +#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) + +/* + * TRBS_PER_SEGMENT must be a multiple of 4, + * since the command ring is 64-byte aligned. + * It must also be greater than 16. + */ +#define TRBS_PER_SEGMENT 64 +/* Allow two commands + a link TRB, along with any reserved command TRBs */ +#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) +#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) +/* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). + * Change this if you change TRBS_PER_SEGMENT! + */ +#define SEGMENT_SHIFT 10 +/* TRB buffer pointers can't cross 64KB boundaries */ +#define TRB_MAX_BUFF_SHIFT 16 +#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) + +struct xhci_segment { + union xhci_trb *trbs; + /* private to HCD */ + struct xhci_segment *next; +}; + +struct xhci_td { + struct list_head td_list; + struct list_head cancelled_td_list; + struct urb *urb; + struct xhci_segment *start_seg; + union xhci_trb *first_trb; + union xhci_trb *last_trb; +}; + +struct xhci_dequeue_state { + struct xhci_segment *new_deq_seg; + union xhci_trb *new_deq_ptr; + volatile int new_cycle_state; +}; + +struct xhci_ring { + struct xhci_segment *first_seg; + union xhci_trb *enqueue; + struct xhci_segment *enq_seg; + unsigned int enq_updates; + union xhci_trb *dequeue; + struct xhci_segment *deq_seg; + unsigned int deq_updates; + struct list_head td_list; + /* + * Write the cycle state into the TRB cycle field to give ownership of + * the TRB to the host controller (if we are the producer), or to check + * if we own the TRB (if we are the consumer). See section 4.9.1. + */ + volatile u32 cycle_state; + volatile unsigned int stream_id; + bool last_td_was_short; +}; + +struct xhci_erst_entry { + /* 64-bit event ring segment address */ + __le64 seg_addr; + __le32 seg_size; + /* Set to zero */ + __le32 rsvd; +}; + +struct xhci_erst { + struct xhci_erst_entry *entries; + unsigned int num_entries; + /* Num entries the ERST can contain */ + unsigned int erst_size; +}; + +struct xhci_scratchpad { + u64 *sp_array; + void **sp_buffers; +}; + +struct urb_priv { + int length; + int td_cnt; + struct xhci_td *td[0]; +}; + +/* + * Each segment table entry is 4*32bits long. 1K seems like an ok size: + * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, + * meaning 64 ring segments. + * Initial allocated size of the ERST, in number of entries */ +#define ERST_NUM_SEGS 3 +/* Initial number of event segment rings allocated */ +#define ERST_ENTRIES 3 +/* Initial allocated size of the ERST, in number of entries */ +#define ERST_SIZE 64 +/* Poll every 60 seconds */ +#define POLL_TIMEOUT 60 +/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ +#define XHCI_STOP_EP_CMD_TIMEOUT 5 +/* XXX: Make these module parameters */ + +struct xhci_virt_ep { + struct xhci_ring *ring; + /* Related to endpoints that are configured to use stream IDs only */ + struct xhci_stream_info *stream_info; + /* Temporary storage in case the configure endpoint command fails + * and we have to restore the device state to the previous state + */ + struct xhci_ring *new_ring; + unsigned int ep_state; +#define SET_DEQ_PENDING (1 << 0) +#define EP_HALTED (1 << 1) /* For stall handling */ +#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ +/* Transitioning the endpoint to using streams, don't enqueue URBs */ +#define EP_GETTING_STREAMS (1 << 3) +#define EP_HAS_STREAMS (1 << 4) +/* Transitioning the endpoint to not using streams, don't enqueue URBs */ +#define EP_GETTING_NO_STREAMS (1 << 5) + /* ---- Related to URB cancellation ---- */ + struct list_head cancelled_td_list; + /* The TRB that was last reported in a stopped endpoint ring */ + union xhci_trb *stopped_trb; + struct xhci_td *stopped_td; + unsigned int stopped_stream; + int stop_cmds_pending; + /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue + * command. We'll need to update the ring's dequeue segment and dequeue + * pointer after the command completes. + */ + struct xhci_segment *queued_deq_seg; + union xhci_trb *queued_deq_ptr; + /* + * Sometimes the xHC can not process isochronous endpoint ring quickly + * enough, and it will miss some isoc tds on the ring and generate + * a Missed Service Error Event. + * Set skip flag when receive a Missed Service Error Event and + * process the missed tds on the endpoint ring. + */ + bool skip; +}; + +#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) + +struct xhci_virt_device { + struct usb_device *udev; + /* + * Commands to the hardware are passed an "input context" that + * tells the hardware what to change in its data structures. + * The hardware will return changes in an "output context" that + * software must allocate for the hardware. We need to keep + * track of input and output contexts separately because + * these commands might fail and we don't trust the hardware. + */ + struct xhci_container_ctx *out_ctx; + /* Used for addressing devices and configuration changes */ + struct xhci_container_ctx *in_ctx; + /* Rings saved to ensure old alt settings can be re-instated */ + /* Store xHC assigned device address */ + int address; +#define XHCI_MAX_RINGS_CACHED 31 + struct xhci_virt_ep eps[31]; + /* Status of the last command issued for this device */ + xhci_comp_code cmd_status; +}; + +/* Interface descriptor */ +struct usb_linux_interface_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bInterfaceNumber; + unsigned char bAlternateSetting; + unsigned char bNumEndpoints; + unsigned char bInterfaceClass; + unsigned char bInterfaceSubClass; + unsigned char bInterfaceProtocol; + unsigned char iInterface; +} __attribute__ ((packed)); + +/* Configuration descriptor */ +struct usb_linux_config_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned short wTotalLength; + unsigned char bNumInterfaces; + unsigned char bConfigurationValue; + unsigned char iConfiguration; + unsigned char bmAttributes; + unsigned char MaxPower; +} __attribute__ ((packed)); + +/* TODO: copied from ehci.h - can be refactored? */ +/* xHCI spec says all registers are little endian */ +static inline unsigned int xhci_readl(uint32_t volatile *regs) +{ + return readl(regs); +} + +static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) +{ + writel(val, regs); +} + +/* Registers should always be accessed with double word or quad word accesses. + * Some xHCI implementations may support 64-bit address pointers. Registers + * with 64-bit address pointers should be written to with dword accesses by + * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. + * xHCI implementations that do not support 64-bit address pointers will ignore + * the high dword, and write order is irrelevant. + */ +static inline u64 xhci_readl_64(__le64 volatile *regs) +{ + __u32 *ptr = (__u32 *) regs; + u64 val_lo = readl(ptr); + u64 val_hi = readl(ptr + 1); + return val_lo + (val_hi << 32); +} + +static inline void xhci_writel_64(__le64 volatile *regs, const u64 val) +{ + __u32 *ptr = (__u32 *) regs; + u32 val_lo = lower_32_bits(val); + /* FIXME */ + u32 val_hi = 0; + writel(val_lo, ptr); + writel(val_hi, ptr + 1); +} + +int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, + struct xhci_hcor **ret_hcor); +void xhci_hcd_stop(int index); + + +/************************************************************* + EXTENDED CAPABILITY DEFINITIONS +*************************************************************/ +/* Up to 16 ms to halt an HC */ +#define XHCI_MAX_HALT_USEC (16*1000) +/* HC not running - set to 1 when run/stop bit is cleared. */ +#define XHCI_STS_HALT (1 << 0) + +/* HCCPARAMS offset from PCI base address */ +#define XHCI_HCC_PARAMS_OFFSET 0x10 +/* HCCPARAMS contains the first extended capability pointer */ +#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) + +/* Command and Status registers offset from the Operational Registers address */ +#define XHCI_CMD_OFFSET 0x00 +#define XHCI_STS_OFFSET 0x04 + +#define XHCI_MAX_EXT_CAPS 50 + +/* Capability Register */ +/* bits 7:0 - how long is the Capabilities register */ +#define XHCI_HC_LENGTH(p) (((p) >> 00) & 0x00ff) + +/* Extended capability register fields */ +#define XHCI_EXT_CAPS_ID(p) (((p) >> 0) & 0xff) +#define XHCI_EXT_CAPS_NEXT(p) (((p) >> 8) & 0xff) +#define XHCI_EXT_CAPS_VAL(p) ((p) >> 16) +/* Extended capability IDs - ID 0 reserved */ +#define XHCI_EXT_CAPS_LEGACY 1 +#define XHCI_EXT_CAPS_PROTOCOL 2 +#define XHCI_EXT_CAPS_PM 3 +#define XHCI_EXT_CAPS_VIRT 4 +#define XHCI_EXT_CAPS_ROUTE 5 +/* IDs 6-9 reserved */ +#define XHCI_EXT_CAPS_DEBUG 10 +/* USB Legacy Support Capability - section 7.1.1 */ +#define XHCI_HC_BIOS_OWNED (1 << 16) +#define XHCI_HC_OS_OWNED (1 << 24) + +/* USB Legacy Support Capability - section 7.1.1 */ +/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ +#define XHCI_LEGACY_SUPPORT_OFFSET (0x00) + +/* USB Legacy Support Control and Status Register - section 7.1.2 */ +/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ +#define XHCI_LEGACY_CONTROL_OFFSET (0x04) +/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ +#define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) + +/* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ +#define XHCI_L1C (1 << 16) + +/* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ +#define XHCI_HLC (1 << 19) + +/* command register values to disable interrupts and halt the HC */ +/* start/stop HC execution - do not write unless HC is halted*/ +#define XHCI_CMD_RUN (1 << 0) +/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ +#define XHCI_CMD_EIE (1 << 2) +/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ +#define XHCI_CMD_HSEIE (1 << 3) +/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ +#define XHCI_CMD_EWE (1 << 10) + +#define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) + +/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ +#define XHCI_STS_CNR (1 << 11) + +struct xhci_ctrl { + struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ + struct xhci_hcor *hcor; + struct xhci_doorbell_array *dba; + struct xhci_run_regs *run_regs; + struct xhci_device_context_array *dcbaa \ + __attribute__ ((aligned(ARCH_DMA_MINALIGN))); + struct xhci_ring *event_ring; + struct xhci_ring *cmd_ring; + struct xhci_ring *transfer_ring; + struct xhci_segment *seg; + struct xhci_intr_reg *ir_set; + struct xhci_erst erst; + struct xhci_erst_entry entry[ERST_NUM_SEGS]; + union xhci_trb trb; + struct xhci_virt_device *devs[MAX_HC_SLOTS]; + int rootdev; + int slot_id; + int port_id; + uint16_t portreset; + u8 *port_array; + int speed; + unsigned int handle_portStatus_Flag; +}; + +unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb); +int xhci_address_device(struct usb_device *usbdev); +void xhci_poll_and_HandleEvent(struct usb_device *usbdev); +int xhci_alloc_dev(struct usb_device *usbdev); +struct xhci_input_control_ctx + *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); +void xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx, + struct xhci_container_ctx *out_ctx); +struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *ctx); +void xhci_endpoint_copy(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *in_ctx, + struct xhci_container_ctx *out_ctx, + unsigned int ep_index); + +#endif /* HOST_XHCI_H_ */