On 4/1/20 12:24 PM, Patrick DELAUNAY wrote:
Hi Gerald and Manivannan,
Hi,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 19:52
The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which can not easily divide the clock down to e.g. 50 MHz for high speed SD and eMMC devices, so those devices end up running at 30 MHz as that is 120 MHz / 4. Adjust the PLL4 settings such that both PLL4P and PLL4R run at 100 MHz instead, which is easy to divide to 50MHz for optimal operation of both SD and eMMC, SPDIF clock are not that much slower and FDCAN is also unaffected.
Reviewed-by: Patrice Chotard patrice.chotard@st.com Reviewed-by: Patrick Delaunay patrick.delaunay@st.com Signed-off-by: Marek Vasut marex@denx.de Cc: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: Move this patch before the split of AV96 into SoM and carrier V3: No change
This patch update the PLL4 frequency used on AV96 board, with different of reference clock tree used on ST board, this new setting allow to optimize the SDMMC frequency (50MHz vs 30Mz).
I don't know why the previous PLL4 frequency was chosen as a compromise on reference clock-tree (PLL4 is used by mostly all the peripheral, with display and audio requirements).
Can you cross check the proposed clock tree and ack this patch if these ST requirements are not applicable on AV96 board.
Anyway the code is correct.
Likely because these PLL settings are being copied from reference platform to other platforms etc.
But I did notice one odd thing, which is when running the SD1 in SDR104, the read data transfers can be unstable, which I suspect is because the bus runs at actual 100 MHz instead of some 60 MHz. I need to look at that with a scope, so that's to be checked. For now I turned the SDR104 off.