Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate
Hi Peng,
Export the structure for others to use.
Signed-off-by: Peng Fan peng.fan@nxp.com
drivers/clk/clk_fixed_rate.c | 8 +------- include/linux/clk-provider.h | 7 +++++++ 2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 089f060a23..069e643fbc 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -6,13 +6,7 @@ #include <common.h> #include <clk-uclass.h> #include <dm.h>
-struct clk_fixed_rate {
- struct clk clk;
- unsigned long fixed_rate;
-};
-#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev)) +#include <linux/clk-provider.h>
static ulong clk_fixed_rate_get_rate(struct clk *clk) { diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 3ed0db86d2..b2bed768b6 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -112,6 +112,13 @@ struct clk_fixed_factor { #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\ clk)
+struct clk_fixed_rate {
- struct clk clk;
- unsigned long fixed_rate;
+};
I think that this struct shall stay where it was. Moreover, the clk-provider.h is not the API to be used by other parts of the clock API.
The clk_fixed_rate shall be accessed via get_rate() only and in IMX6Q it is available in early SPL (parsed from dts /clocks property - the 24MHz OSC)
+#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev)) + int clk_register(struct clk *clk, const char *drv_name, ulong drv_data, const char *name, const char *parent_name);
Please explain why iMX8MM needs such global export?
In clk-imx8mm.c, first configure ARM clk to osc24M fixed clk to change pll clock. + /* Configure ARM to osc24M */ + clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp); + uclass_get_device_by_name(UCLASS_CLK, "clock-osc-24m", &devp); + clkp1 = &to_clk_fixed_rate(devp)->clk; + clk_set_parent(clkp, clkp1); + + /* Configure ARM PLL to 1.2GHz */ + clk_get_by_id(IMX8MM_ARM_PLL, &clkp1); + clk_set_rate(clkp1, 1200000000UL); + clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1); + clk_enable(clkp1); + clk_set_parent(clkp, clkp1); + + /* Configure DIV to 1.2GHz */ + clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1); + clk_set_rate(clkp1, 1200000000UL);
Regards, Peng.
Best regards,
Lukasz Majewski
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