Hi Marek,
What do you mean by this ? Is your ethernet controller synthesised in the FPGA ? The arriaV socdk u-boot uses the top-side ethernet port, which is connected to the ethernet controller in the HPS.
I managed to get it working. Right after configuring fpga from Linux I made a soft reset and PHY chip was successfully found.
Net: eth0: ethernet@ff702000
However there is still no ping in U-Boot. After power reset I did:
# bridge disable # fpga load 0 <addr> <size> # bridge enable
# md 0xff706000 1
ff706000: 00000074 <-- this means fpga is in user mode
# setenv ethaddr ... # setenv ipaddr ... # setenv netmask ... # setenv gatewayip ...
=> ping 192.168.1.126 Speed: 100, full duplex Using ethernet@ff702000 device ping failed; host 192.168.1.126 is not alive
With similar commands on previous U-Boot version I had ping.
Best regards, Denis Bakhvalov