Add dram config macro for handling cs1 column.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: YouMin Chen cym@rock-chips.com --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 3 +++ drivers/ram/rockchip/sdram_rk3399.c | 1 + 2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index dc7275656e..637a0de902 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -74,6 +74,9 @@ (4 + 2 * (ch)); \ } while (0)
+#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch)) +#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch)) + /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 772fde9732..d77a8310cd 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1033,6 +1033,7 @@ static void dram_all_config(struct dram_info *dram, if (info->cs1_row) SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2, sys_reg3, channel); + sys_reg3 |= SYS_REG_ENC_CS1_COL(info->col, channel);
ddr_msch_regs = dram->chan[channel].msch; noc_timing = &sdram_params->ch[channel].noc_timings;