----- "Pantelis Antoniou" panto@antoniou-consulting.com wrote:
Hi Ajay,
On Sep 24, 2013, at 11:02 AM, Ajay Bhargav wrote:
This patch add SD/MMC interface register difinitions for Armada100 series.
Signed-off-by: Ajay Bhargav ajay.bhargav@einfochips.com
arch/arm/include/asm/arch-armada100/armada100.h | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index d9feb16..81e4b8a 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -27,6 +27,14 @@ #define SSP2_APBCLK 0x01 #define SSP2_FNCLK 0x02
+/* SD Clock/Reset Control Register Bit definition */ +#define SD1_SD2_AXI_RESET 0x01 +#define SD1_RESET 0x02 +#define SD1_SD2_AXICLK_EN 0x08 +#define SD1_CLK_EN 0x10 +#define SD2_RESET 0x02 +#define SD2_CLK_EN 0x10
/* USB Clock/reset control bits */ #define USB_SPH_AXICLK_EN 0x10 #define USB_SPH_AXI_RST 0x02 @@ -53,6 +61,8 @@ #define ARMD1_UART3_BASE 0xD4026000 #define ARMD1_MPMU_BASE 0xD4050000 #define ARMD1_USB_HOST_BASE 0xD4209000 +#define ARMD1_SD1_BASE 0xD4280000 +#define ARMD1_SD2_BASE 0xD4281000 #define ARMD1_APMU_BASE 0xD4282800 #define ARMD1_CPU_BASE 0xD4282C00
-- 1.8.3.rc3
Looks fine.
Acked-by: Pantelis Antoniou panto@antoniou-consulting.com
Hi Pantelis,
May I know, when are you going to update u-boot-mmc custodian?
Regards, Ajay Bhargav
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