Dear Marek Vasut,
Dear Andreas Puls,
Hi together,
i've got another problem with latest stable U-Boot-2012.10 and a Toradex Colibri PXA270 V2.4
Uboot dosen't regonized the CPU Revision u-boot summary screen:
U-Boot 2012.10 (Nov 12 2012 - 14:22:12) CPU: Marvell PXA27x rev. Unknown
See arch/arm/cpu/pxa/cpuinfo.c , patch is welcome ... they probably rolled out some new CPU version.
Yes, its a PXA270 M. There is a spec. update pdf from Marvel. http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec... - Table 2-3.
They changed the Stepping from A0...C5 to "PXA270M -- A1" A colleague would support me to change this becouse i have no cloue about writing C Files. So we would like ask you first if the right CPU Name should be shown in the summary screen which would be a rewrite of your function or only the right stepping with the old CPU Name would be enough ? (Damn it - hope you understand my Denglish)
first lines of dmesg: [ 0.000000] CPU: XScale-PXA270 [69054118] revision 8 (ARMv5TE), cr=0000397f [ 0.000000] CPU: VIVT data cache, VIVT instruction cache [ 0.000000] Machine: Toradex Colibri PXA270 [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] Run Mode clock: 208.00MHz (*16) [ 0.000000] Turbo Mode clock: 520.00MHz (*2.5, inactive) [ 0.000000] Memory clock: 104.00MHz (/2) [ 0.000000] System bus clock: 104.00MHz
Looks like you need to enable the "Turbo" bit, patch is welcome. See arch/arm/cpu/pxa/start.S and arch/arm/cpu/pxa/pxa2xx.c
Thank you for the files where we can look up. We will try.
$ cat /proc/cpuinfo Processor : XScale-PXA270 rev 8 (v5l) BogoMIPS : 207.66 Features : swp half thumb fastmult edsp iwmmxt CPU implementer : 0x69 CPU architecture: 5TE CPU variant : 0x0 CPU part : 0x411 CPU revision : 8
Hardware : Toradex Colibri PXA270 Revision : 0000 Serial : 0000000000000000
[...] Kind regards Andreas
Best regards, Marek Vasut
Kind regards Andreas