Hi Stefan,
On Fri, Mar 1, 2013 at 5:20 PM, Stefan Roese sr@denx.de wrote:
On 01.03.2013 12:23, Jagannadha Sutradharudu Teki wrote:
This commit is based on that patch from aaron.williams@caviumnetworks.com with same commit along with few code cleanup changes.
This patch corrects the addresses used when working with Spansion/AMD FLASH chips. Addressing for 8 and 16 bits is almost identical except in the 16-bit case the LSB of the address is always 0. The confusion arose because the addresses in the datasheet for 16-bit mode are word addresses but this code assumed it was byte addresses.
I have only been able to test this on our Octeon boards which use either an 8-bit or 16-bit bus. I have not tested the case where there's an 8-bit part on a 16-bit bus.
This patch also adds some delays as suggested by Spansion.
If a part can be both 8 and 16-bits, it forces it to work in 8-bit mode if an 8-bit bus is detected.
Before this fix:
Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0xFF, Device ID: 0xFF Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes
After this fix:
Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x89, Device ID: 0x7E2301 Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes
Tested on: 256M29EW, 512M29EW flashes.
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Tested-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com
Please preserve the previous commit text and the S-o-b lines for patch authorship. And add your comments with the additions to this text. And finally your S-o-b as well of course.
OK, can send with the same version v3?
Thanks, Jagan.
Thanks, Stefan
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