Since your commit broke my platform to fix yours, shouldn't it be reverted and TI platforms use your pending patch queue?
On Dec 3, 2017 23:14, "Vignesh R" vigneshr@ti.com wrote:
On Sunday 03 December 2017 09:29 PM, Frank Mori Hess wrote:
This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
My u-boot spl crashes in a loop when I boot off a cadence qspi flash. I narrowed it down to the changes from commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1 which removes CQSPI_INDIRECTTRIGGER_ADDR_MASK. Restoring the mask allows the spl to successfully load the main u-boot. My board is an Altera HPS cyclone V socfpga. It has an ahb base address of 0xffa00000 and for some reason, without the CQSPI_INDIRECTTRIGGER_ADDR_MASK the board reboots when cadence_qspi_apb_indirect_read_execute tries to read from the ahb base address. I'm was using version 2016.11 of u-boot.
This breaks TI platforms where INDIRECTTRIGGER_ADDR is 32bit wide. Instead please try this patch series which adds cdns,trigger-address DT property: http://patchwork.ozlabs.org/patch/838589/
Regards Vignesh
Signed-off-by: Frank Mori Hess fmh6jj@gmail.com
drivers/spi/cadence_qspi_apb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb
.c
index e02f2217f4..b300f36607 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -47,6 +47,7 @@ #define CQSPI_INST_TYPE_QUAD 2
#define CQSPI_STIG_DATA_LEN_MAX 8 +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK 0xFFFFF
#define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 @@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct
cadence_spi_platdata *plat,
addr_bytes = cmdlen - 1; /* Setup the indirect trigger address */
writel((u32)plat->ahbbase,
writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */@@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct
cadence_spi_platdata *plat,
return -EINVAL; } /* Setup the indirect trigger address */
writel((u32)plat->ahbbase,
writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */