Hi Liberty,
I am already knee deep in adding Altera Stratix II support to the u-boot via the fpga command (currently xlinix & acex1k are supported)...
of course I will re-post when i am done.
My only question is,
Am i reinventing the wheel? Is it already implemented anywhere?
If i am, where can I find a reference to the work already done?
If not I will soon give you one :)
I haven't looked for it yet, but I plan to add support too eventually (= months from now when I get boards).
I haven't looked at the code, but here's how I plan to configure my FPGAs. Your method may be different, so perhaps between us we can come up with a consistent API.
The board I am designing will contain an MPC8349E, and Altera Stratix II system controller FPGA on the processor local bus, and then 4 other programmable FPGAs. A board placement PDF is here;
http://www.ovro.caltech.edu/~dwh/carma_board/carma_board_placement.pdf
and engineering documents are here
http://www.ovro.caltech.edu/~dwh/carma_board/
The system controller FPGA will boot from Flash, a MAX II CPLD will configure it on power-up, and then it'll bring the PPC out of reset, which will then boot through Flash located off the system controller FPGA (hence the system controller comes to life before the processor). The other four FPGAs will be programmed as the application dictates.
So given U-Boot running, I'd imagine tftp'ing RBF (raw binary format) files generated by Quartus over to the board. I'd then copy the files to a block of memory which maps in my system controller to a fast-passive-parallel (FPP) programmer. That state machine then programs the FPGAs. In Linux the same procedure would be hidden behind a driver so I could dd the RBFs into /dev/fgpa_fpp or /sys/.../firmware.
The point of mapping the FPP programmer into a block of local bus memory addresses is so that I can use the MPC8349E DMA controller to DMA the RBF files from SDRAM memory to the programmer memory (eg. from files in a RAM filesystem). According to the datasheet MPC8349E DMA controller won't burst with a fixed destination address (FIFO mode), so I'll just fake it out and let it DMA to what it thinks is an incrementing address location.
How are you planning on programming your FPGA?
Cheers Dave