Re: [U-Boot] [PATCH] nds32: mmc: Support ftsdc010 DM.

Hi,

On 05/24/2017 10:47 AM, Andes wrote:

From: rick rick@andestech.com

Support Andestech ftsdc010 SD/MMC device tree flow on AG101P/AE3XX platforms. Verification : boot linux kernel from sd card

Split the patch...

NDS32 # mmc rescan NDS32 # fatls mmc 0:1 13938796 boomimage-310y-ag101p.bin

1 file(s)

NDS32 # fatload mmc 0:1 0x600000 boomimage-310y-ag101p.bin reading boomimage-310y-ag101p.bin 13938796 bytes read in 17358 ms (784.2 KiB/s) NDS32 # bootm 0x600000 Image Name: Created: 2017-05-23 1:58:24 UTC Image Type: NDS32 Linux Kernel Image (uncompressed) Data Size: 13938732 Bytes = 13.3 MiB Load Address: 0000c000 Entry Point: 0000c000 Verifying Checksum ... OK Loading Kernel Image ... OK Linux version 3.10.102-20420-g301b0f6 (rick@app09) (gcc version 4.9.3 (2016-07-06_nds32le-linux-glibc-v3_experimental) )#798 PREEMPT Tue May 23 09:57:59 CST 2017 CPU: NDS32 N13, AndesCore ID(wb), CPU_VER 0x0d0c003f(id 13, rev 12, cfg 63) ... ... Signed-off-by: rick rick@andestech.com

---

arch/nds32/dts/ae3xx.dts | 8 ++ arch/nds32/dts/ag101p.dts | 8 ++ board/AndesTech/adp-ae3xx/adp-ae3xx.c | 4 +- board/AndesTech/adp-ag101p/adp-ag101p.c | 7 +- configs/adp-ae3xx_defconfig | 5 ++ configs/adp-ag101p_defconfig | 5 ++ drivers/mmc/Kconfig | 12 +++ drivers/mmc/Makefile | 1 + drivers/mmc/ftsdc010_mci.c | 140 ++++++++++++++++++++++++------- drivers/mmc/ftsdc010_mci.h | 54 ++++++++++++ drivers/mmc/nds32_mmc.c | 139 ++++++++++++++++++++++++++++++ include/configs/adp-ae3xx.h | 1 - include/configs/adp-ag101p.h | 1 - 13 files changed, 344 insertions(+), 41 deletions(-) create mode 100644 drivers/mmc/ftsdc010_mci.h create mode 100644 drivers/mmc/nds32_mmc.c

diff --git a/arch/nds32/dts/ae3xx.dts b/arch/nds32/dts/ae3xx.dts index 4221e4b..781eabc 100644 --- a/arch/nds32/dts/ae3xx.dts +++ b/arch/nds32/dts/ae3xx.dts @@ -62,6 +62,14 @@ interrupts = <25 4>; };

• mmc0: mmc@f0e00000 {

• compatible = "andestech,atsdc010";
  

• clock-freq-min-max = <400000 100000000>;
  

• fifo-depth = <0x10>;
  

• reg = <0xf0e00000 0x1000>;
  

• interrupts = <17 4>;
  

• };
• nor@0,0 { compatible = "cfi-flash"; reg = <0x88000000 0x1000>;

diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts index 99cde2f..dd2bf8f 100644 --- a/arch/nds32/dts/ag101p.dts +++ b/arch/nds32/dts/ag101p.dts @@ -60,4 +60,12 @@ reg = <0x90900000 0x1000>; interrupts = <25 4>; };

• mmc0: mmc@98e00000 {

• compatible = "andestech,atsdc010";
  

• clock-freq-min-max = <400000 30000000>;
  

• fifo-depth = <0x10>;
  

• reg = <0x98e00000 0x1000>;
  

• interrupts = <5 4>;
  

• };

}; diff --git a/board/AndesTech/adp-ae3xx/adp-ae3xx.c b/board/AndesTech/adp-ae3xx/adp-ae3xx.c index 98ed4d9..3903427 100644 --- a/board/AndesTech/adp-ae3xx/adp-ae3xx.c +++ b/board/AndesTech/adp-ae3xx/adp-ae3xx.c @@ -77,10 +77,8 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)

int board_mmc_init(bd_t *bis) { -#ifndef CONFIG_DM_MMC -#ifdef CONFIG_FTSDC010 +#if defined(CONFIG_FTSDC010) && !defined(CONFIG_DM_MMC) ftsdc010_mmc_init(0); #endif -#endif return 0; } diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c index a462941..826ba14 100644 --- a/board/AndesTech/adp-ag101p/adp-ag101p.c +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -20,7 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; /*

• Miscellaneous platform dependent initializations

*/

int board_init(void) { /* @@ -30,7 +29,6 @@ int board_init(void) printf("Board: %s\n" , CONFIG_SYS_BOARD); gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P; gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;

• return 0;

}

@@ -39,11 +37,8 @@ int dram_init(void) unsigned long sdram_base = PHYS_SDRAM_0; unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; unsigned long actual_size;

• actual_size = get_ram_size((void *)sdram_base, expected_size);
• gd->ram_size = actual_size;
• if (expected_size != actual_size) { printf("Warning: Only %lu of %lu MiB SDRAM is working\n", actual_size >> 20, expected_size >> 20);

@@ -83,7 +78,7 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)

int board_mmc_init(bd_t *bis) { -#ifdef CONFIG_FTSDC010 +#if defined(CONFIG_FTSDC010) && !defined(CONFIG_DM_MMC) ftsdc010_mmc_init(0); #endif return 0; diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig index cbef412..d12f307 100644 --- a/configs/adp-ae3xx_defconfig +++ b/configs/adp-ae3xx_defconfig @@ -18,6 +18,11 @@ CONFIG_BAUDRATE=38400 CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_BLK=y +CONFIG_DM_MMC=y +CONFIG_DM_MMC_OPS=y +CONFIG_MMC_NDS32=y +CONFIG_FTSDC010=y CONFIG_MTD=y CONFIG_CFI_FLASH=y CONFIG_DM_ETH=y diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig index 22b1182..85e2225 100644 --- a/configs/adp-ag101p_defconfig +++ b/configs/adp-ag101p_defconfig @@ -18,6 +18,11 @@ CONFIG_BAUDRATE=38400 CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_BLK=y +CONFIG_DM_MMC=y +CONFIG_DM_MMC_OPS=y +CONFIG_MMC_NDS32=y +CONFIG_FTSDC010=y CONFIG_DM_ETH=y CONFIG_FTMAC100=y CONFIG_DM_SERIAL=y diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0dd4443..ca1376a 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -377,6 +377,18 @@ config GENERIC_ATMEL_MCI the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.

+config MMC_NDS32

• bool "Andestech SD/MMC controller support"
• depends on DM_MMC && OF_CONTROL
• help

•  This enables support for the Andestech SD/MMM controller, which is
  

•  based on Faraday IP.
  

+config FTSDC010

• bool "Ftsdc010 SD/MMC controller Support"
• help

•  This SD/MMC controller is present in Andestech SoCs which is based on Faraday IP.
  

endif

config TEGRA124_MMC_DISABLE_EXT_LOOPBACK diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index a078649..08a552a 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_S3C_SDI) += s3c_sdi.o obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SH_SDHI) += sh_sdhi.o +obj-$(CONFIG_MMC_NDS32) += nds32_mmc.o

# SDHCI obj-$(CONFIG_MMC_SDHCI) += sdhci.o diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 652a718..ec0bc6b 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -12,24 +12,15 @@ #include <part.h> #include <mmc.h>

-#include <asm/io.h> +#include <linux/io.h> #include <linux/errno.h> #include <asm/byteorder.h> #include <faraday/ftsdc010.h> +#include "ftsdc010_mci.h"

#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */

-struct ftsdc010_chip {

• void __iomem *regs;
• uint32_t wprot; /* write protected (locked) */
• uint32_t rate; /* actual SD clock in Hz */
• uint32_t sclk; /* FTSDC010 source clock in Hz */
• uint32_t fifo; /* fifo depth in bytes */
• uint32_t acmd;
• struct mmc_config cfg; /* mmc configuration */

-};

static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) { struct ftsdc010_chip *chip = mmc->priv; @@ -127,9 +118,8 @@ static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate) static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) { int ret = -ETIMEDOUT;

• uint32_t st, ts;
• for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {

• uint32_t st, timeout = 10000000;
• while (timeout--) { st = readl(&regs->status); if (!(st & mask)) continue;

@@ -147,10 +137,16 @@ static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) /*

• u-boot mmc api

*/

+#ifdef CONFIG_DM_MMC_OPS +static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,

• struct mmc_data *data)

+{

• struct mmc *mmc = mmc_get_mmc_dev(dev);

+#else static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { +#endif int ret = -EOPNOTSUPP; uint32_t len = 0; struct ftsdc010_chip *chip = mmc->priv; @@ -251,8 +247,14 @@ static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd, return ret; }

+#ifdef CONFIG_DM_MMC_OPS +static int ftsdc010_set_ios(struct udevice *dev) +{

• struct mmc *mmc = mmc_get_mmc_dev(dev);

+#else static int ftsdc010_set_ios(struct mmc *mmc) { +#endif struct ftsdc010_chip *chip = mmc->priv; struct ftsdc010_mmc __iomem *regs = chip->regs;

@@ -274,20 +276,46 @@ static int ftsdc010_set_ios(struct mmc *mmc) return 0; }

-static int ftsdc010_init(struct mmc *mmc) +#ifdef CONFIG_DM_MMC_OPS +static int ftsdc010_get_cd(struct udevice *dev) {

• struct mmc *mmc = mmc_get_mmc_dev(dev);

+#else +static int ftsdc010_getcd(struct mmc *mmc) +{ +#endif struct ftsdc010_chip *chip = mmc->priv; struct ftsdc010_mmc __iomem *regs = chip->regs;

• uint32_t ts;
• if (readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT)

• return -ENOMEDIUM;
  

• return 0;
  

• return 1;

+}

+#ifdef CONFIG_DM_MMC_OPS +static int ftsdc010_get_wp(struct udevice *dev) +{

• struct mmc *mmc = mmc_get_mmc_dev(dev);

+#else +static int ftsdc010_getwp(struct mmc *mmc) +{ +#endif

• struct ftsdc010_chip *chip = mmc->priv;

• struct ftsdc010_mmc __iomem *regs = chip->regs; if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) { printf("ftsdc010: write protected\n"); chip->wprot = 1; }

• return 0;

+}

+static int ftsdc010_init(struct mmc *mmc) +{

• struct ftsdc010_chip *chip = mmc->priv;

• struct ftsdc010_mmc __iomem *regs = chip->regs;

• uint32_t ts;

• chip->fifo = (readl(&regs->feature) & 0xff) << 2;

  /* 1. chip reset */

@@ -311,11 +339,70 @@ static int ftsdc010_init(struct mmc *mmc) return 0; }

+#ifdef CONFIG_DM_MMC_OPS +int ftsdc010_probe(struct udevice *dev) +{

• struct mmc *mmc = mmc_get_mmc_dev(dev);
• return ftsdc010_init(mmc);

+}

+const struct dm_mmc_ops dm_ftsdc010_ops = {

• .send_cmd = ftsdc010_request,
• .set_ios = ftsdc010_set_ios,
• .get_cd = ftsdc010_get_cd,
• .get_wp = ftsdc010_get_wp,

+};

+#else static const struct mmc_ops ftsdc010_ops = { .send_cmd = ftsdc010_request, .set_ios = ftsdc010_set_ios,

• .getcd = ftsdc010_getcd,
• .getwp = ftsdc010_getwp, .init = ftsdc010_init,

}; +#endif

+void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,

•      uint caps, u32 max_clk, u32 min_clk)
  

+{

• cfg->name = name;
• cfg->f_min = min_clk;
• cfg->f_max = max_clk;
• cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
• cfg->host_caps = caps;
• if (buswidth == 8) {

• cfg->host_caps |= MMC_MODE_8BIT;
  

• cfg->host_caps &= ~MMC_MODE_4BIT;
  

• } else {

• cfg->host_caps |= MMC_MODE_4BIT;
  

• cfg->host_caps &= ~MMC_MODE_8BIT;
  

• }
• cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
• cfg->part_type = PART_TYPE_DOS;
• cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

+}

+void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg) +{

• switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) {
• case FTSDC010_BWR_CAPS_4BIT:

• cfg->host_caps |= MMC_MODE_4BIT;
  

• break;
  

• case FTSDC010_BWR_CAPS_8BIT:

• cfg->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
  

• break;
  

• default:

• break;
  

• }

+}

+#ifdef CONFIG_BLK +int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) +{

• return mmc_bind(dev, mmc, cfg);

+} +#else

int ftsdc010_mmc_init(int devid) { @@ -345,19 +432,11 @@ int ftsdc010_mmc_init(int devid) #endif

chip->cfg.name = "ftsdc010"; +#ifndef CONFIG_DM_MMC_OPS chip->cfg.ops = &ftsdc010_ops; +#endif chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;

• switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) {
• case FTSDC010_BWR_CAPS_4BIT:

• chip->cfg.host_caps |= MMC_MODE_4BIT;
  

• break;
  

• case FTSDC010_BWR_CAPS_8BIT:

• chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
  

• break;
  

• default:

• break;
  

• }

• set_bus_width(regs , &chip->cfg); chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; chip->cfg.f_max = chip->sclk / 2; chip->cfg.f_min = chip->sclk / 0x100;

@@ -373,3 +452,4 @@ int ftsdc010_mmc_init(int devid)

return 0; } +#endif diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h new file mode 100644 index 0000000..f74015e --- /dev/null +++ b/drivers/mmc/ftsdc010_mci.h @@ -0,0 +1,54 @@ +/*

• • Faraday FTSDC010 Secure Digital Memory Card Host Controller
• • Copyright (C) 2011 Andes Technology Corporation
• • Macpaul Lin, Andes Technology Corporation macpaul@andestech.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <mmc.h>

+#ifndef __FTSDC010_MCI_H +#define __FTSDC010_MCI_H

+struct ftsdc010_chip {

• void __iomem *regs;
• uint32_t wprot; /* write protected (locked) */
• uint32_t rate; /* actual SD clock in Hz */
• uint32_t sclk; /* FTSDC010 source clock in Hz */
• uint32_t fifo; /* fifo depth in bytes */
• uint32_t acmd;
• struct mmc_config cfg; /* mmc configuration */
• const char *name;
• void *ioaddr;
• unsigned int quirks;
• unsigned int caps;
• unsigned int version;
• unsigned int clock;
• unsigned int bus_hz;
• unsigned int div;
• int dev_index;
• int dev_id;
• int buswidth;
• u32 fifoth_val;
• struct mmc *mmc;
• void *priv;
• bool fifo_mode;

+};

+#ifdef CONFIG_DM_MMC_OPS +/* Export the operations to drivers */ +int ftsdc010_probe(struct udevice *dev); +extern const struct dm_mmc_ops dm_ftsdc010_ops; +#endif +void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,

•      uint caps, u32 max_clk, u32 min_clk);
  

+void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg);

+#ifdef CONFIG_BLK +int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); +#endif

+#endif /* __FTSDC010_MCI_H */ diff --git a/drivers/mmc/nds32_mmc.c b/drivers/mmc/nds32_mmc.c new file mode 100644 index 0000000..ec25fe9 --- /dev/null +++ b/drivers/mmc/nds32_mmc.c @@ -0,0 +1,139 @@ +/*

• • Andestech ATFSDC010 SD/MMC driver
• • (C) Copyright 2016
• • Rick Chen, NDS32 Software Engineering, rick@andestech.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-structs.h> +#include <faraday/ftsdc010.h> +#include <errno.h> +#include <mapmem.h> +#include <pwrseq.h> +#include <syscon.h> +#include <mmc.h> +#include <linux/err.h> +#include "ftsdc010_mci.h"

+DECLARE_GLOBAL_DATA_PTR;

+#if CONFIG_IS_ENABLED(OF_PLATDATA) +struct nds_mmc {

• fdt32_t bus_width;
• bool cap_mmc_highspeed;
• bool cap_sd_highspeed;
• fdt32_t card_detect_delay;
• fdt32_t clock_freq_min_max[2];
• struct phandle_2_cell clocks[4];
• bool disable_wp;
• fdt32_t fifo_depth;
• fdt32_t interrupts[3];
• fdt32_t num_slots;
• fdt32_t reg[2];
• fdt32_t vmmc_supply;

+}; +#endif

+struct nds_mmc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA)

• struct nds_mmc dtplat;

+#endif

• struct mmc_config cfg;
• struct mmc mmc;

+};

+struct ftsdc_priv {

• struct clk clk;
• struct ftsdc010_chip chip;
• int fifo_depth;
• bool fifo_mode;
• u32 minmax[2];

+};

+static int nds32_mmc_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA)

• struct ftsdc_priv *priv = dev_get_priv(dev);
• struct ftsdc010_chip *chip = &priv->chip;
• chip->name = dev->name;
• chip->ioaddr = (void *)dev_get_addr(dev);
• chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,

• 			"bus-width", 4);
  

• chip->priv = dev;
• /* use non-removeable as sdcard and emmc as judgement */
• if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))

• chip->dev_index = 0;
  

• else

• chip->dev_index = 1;
  

• priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,

• 		    "fifo-depth", 0);
  

• priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,

• 			  "fifo-mode");
  

• if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,

• 		 "clock-freq-min-max", priv->minmax, 2))
  

• return -EINVAL;
  

+#endif

• chip->sclk = priv->minmax[1];
• chip->regs = chip->ioaddr;
• return 0;

+}

+static int nds32_mmc_probe(struct udevice *dev) +{

• struct nds_mmc_plat *plat = dev_get_platdata(dev);
• struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
• struct ftsdc_priv *priv = dev_get_priv(dev);
• struct ftsdc010_chip *chip = &priv->chip;
• struct udevice *pwr_dev __maybe_unused;

+#if CONFIG_IS_ENABLED(OF_PLATDATA)

• int ret;
• struct nds_mmc *dtplat = &plat->dtplat;
• chip->name = dev->name;
• chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
• chip->buswidth = dtplat->bus_width;
• chip->priv = dev;
• chip->dev_index = 0;
• priv->fifo_depth = dtplat->fifo_depth;
• priv->fifo_mode = 0;
• memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
• ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
• if (ret < 0)

• return ret;
  

+#endif

• ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,

• 	priv->minmax[1] , priv->minmax[0]);
  

• chip->mmc = &plat->mmc;
• chip->mmc->priv = &priv->chip;
• chip->mmc->dev = dev;
• upriv->mmc = chip->mmc;
• return ftsdc010_probe(dev);

+}

+static int nds32_mmc_bind(struct udevice *dev) +{

• struct nds_mmc_plat *plat = dev_get_platdata(dev);
• return ftsdc010_bind(dev, &plat->mmc, &plat->cfg);

+}

+static const struct udevice_id nds32_mmc_ids[] = {

• { .compatible = "andestech,atsdc010" },
• { }

+};

+U_BOOT_DRIVER(nds32_mmc_drv) = {

• .name = "nds32_mmc",
• .id = UCLASS_MMC,
• .of_match = nds32_mmc_ids,
• .ofdata_to_platdata = nds32_mmc_ofdata_to_platdata,
• .ops = &dm_ftsdc010_ops,
• .bind = nds32_mmc_bind,
• .probe = nds32_mmc_probe,
• .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
• .platdata_auto_alloc_size = sizeof(struct nds_mmc_plat),

+}; diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h index 6bfc08e..011b2a8 100644 --- a/include/configs/adp-ae3xx.h +++ b/include/configs/adp-ae3xx.h @@ -92,7 +92,6 @@ /*

• SD (MMC) controller

*/ -#define CONFIG_FTSDC010 #define CONFIG_FTSDC010_NUMBER 1 #define CONFIG_FTSDC010_SDIO

diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index 4cef64e..71a557b 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -98,7 +98,6 @@ /*

• SD (MMC) controller

*/ -#define CONFIG_FTSDC010 #define CONFIG_FTSDC010_NUMBER 1 #define CONFIG_FTSDC010_SDIO