25 Feb
2004
25 Feb
'04
1:49 p.m.
Wolfgang Denk wrote:
Is CFG_HZ defined for all other architectures?
It is supposed to be defined. But many boards define it incorrectly.
Should we use CFG_HZ instead of hardcoded numbers?
Definitely.
Here we go:
* Patch by Steven Scholz, 25 Feb 2004: - Timeouts in FPGA code should be based on CFG_HZ - Minor cleanup in code for Altera FPGA ACEX1K
BTW: I just noticed that loads of timeouts (e.g. CFG_FLASH_ERASE_TOUT) are _not_ defined using CFG_HZ ...
--
Steven Scholz
imc Measurement & Control imc Meßsysteme GmbH
Voltastr. 5 Voltastr. 5
13355 Berlin 13355 Berlin
Germany Deutschland
Index: common/ACEX1K.c
===================================================================
RCS file: /cvsroot/u-boot/u-boot/common/ACEX1K.c,v
retrieving revision 1.1
diff -p -u -r1.1 ACEX1K.c
--- common/ACEX1K.c 9 Oct 2003 20:09:04 -0000 1.1
+++ common/ACEX1K.c 25 Feb 2004 12:25:36 -0000
@@ -31,17 +31,12 @@
#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
/* Define FPGA_DEBUG to get debug printf's */
-/* #define FPGA_DEBUG */
-
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
-#undef CFG_FPGA_CHECK_BUSY
-#define CFG_FPGA_PROG_FEEDBACK
-
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
@@ -52,7 +47,7 @@
#endif
#ifndef CFG_FPGA_WAIT
-#define CFG_FPGA_WAIT 100
+#define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */
#endif
static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
@@ -162,7 +157,7 @@ static int ACEX1K_ps_load (Altera_desc *
__FUNCTION__, &fn, fn, fn->config, fn->status,
fn->clk, fn->data, fn->done);
#ifdef CFG_FPGA_PROG_FEEDBACK
- printf ("Loading FPGA Device %d (@ %ld)...\n", cookie, ts);
+ printf ("Loading FPGA Device %d...", cookie);
#endif
/*
@@ -246,7 +241,7 @@ static int ACEX1K_ps_load (Altera_desc *
CONFIG_FPGA_DELAY ();
#ifdef CFG_FPGA_PROG_FEEDBACK
- putc ('\n'); /* terminate the dotted line */
+ putc (' '); /* terminate the dotted line */
#endif
/*
Index: common/spartan2.c
===================================================================
RCS file: /cvsroot/u-boot/u-boot/common/spartan2.c,v
retrieving revision 1.3
diff -p -u -r1.3 spartan2.c
--- common/spartan2.c 27 Jun 2003 21:32:32 -0000 1.3
+++ common/spartan2.c 25 Feb 2004 12:25:36 -0000
@@ -47,7 +47,7 @@
#endif
#ifndef CFG_FPGA_WAIT
-#define CFG_FPGA_WAIT 10
+#define CFG_FPGA_WAIT CFG_HZ/100 /* 10 ms */
#endif
static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
Index: common/virtex2.c
===================================================================
RCS file: /cvsroot/u-boot/u-boot/common/virtex2.c,v
retrieving revision 1.1.1.1
diff -p -u -r1.1.1.1 virtex2.c
--- common/virtex2.c 21 Aug 2002 22:08:56 -0000 1.1.1.1
+++ common/virtex2.c 25 Feb 2004 12:25:36 -0000
@@ -80,7 +80,7 @@
* an XC2V1000, if anyone can ever get ahold of one.
*/
#ifndef CFG_FPGA_WAIT_INIT
-#define CFG_FPGA_WAIT_INIT 500 /* time in milliseconds */
+#define CFG_FPGA_WAIT_INIT CFG_HZ/2 /* 500 ms */
#endif
/*
@@ -89,14 +89,14 @@
* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
*/
#ifndef CFG_FPGA_WAIT_BUSY
-#define CFG_FPGA_WAIT_BUSY 5 /* time in milliseconds */
+#define CFG_FPGA_WAIT_BUSY CFG_HZ/200 /* 5 ms*/
#endif
/* Default timeout for waiting for FPGA to enter operational mode after
* configuration data has been written.
*/
#ifndef CFG_FPGA_WAIT_CONFIG
-#define CFG_FPGA_WAIT_CONFIG 200 /* time in milliseconds */
+#define CFG_FPGA_WAIT_CONFIG CFG_HZ/5 /* 200 ms */
#endif
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize);