Some parts lack Bank B in L1 data, so have the linker script fall back to Bank A when that happens. This way we can still leverage L1 data.
Signed-off-by: Mike Frysinger vapier@gentoo.org --- arch/blackfin/lib/u-boot.lds.S | 10 +++++++--- 1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/blackfin/lib/u-boot.lds.S b/arch/blackfin/lib/u-boot.lds.S index f15c97e..2b8d285 100644 --- a/arch/blackfin/lib/u-boot.lds.S +++ b/arch/blackfin/lib/u-boot.lds.S @@ -40,9 +40,13 @@ * This is here in the first place so we can quickly test building * for different CPU's which may lack non-cache L1 data. */ +#ifndef L1_DATA_A_SRAM +# define L1_DATA_A_SRAM 0 +# define L1_DATA_A_SRAM_SIZE 0 +#endif #ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 +# define L1_DATA_B_SRAM L1_DATA_A_SRAM +# define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE #endif
/* The 0xC offset is so we don't clobber the tiny LDR jump block. */ @@ -138,7 +142,7 @@ SECTIONS } >l1_data AT>ram_data __data_l1_lma = LOADADDR(.data_l1); __data_l1_len = SIZEOF(.data_l1); - ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!") + ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!")
.bss : {