On Saturday, October 21, 2006 3:19 AM Stefan Roese wrote:
But please note that bamboo (440EP) is not a perfect example for DDR
init on 440 systems, since it has one bank of DDR soldered onboard _plus_ the DIMM module(s).
I just realized that we have another 440EP board in the U-Boot tree
that
matches your SDRAM setup better. The "pcs440ep". It has one DIMM
module
and no onboard SDRAM.
[Leonid] Actually I could make spd_sdram work for my board (our HW guy hooked up DIMM EEPROM connections for me). I stepped through code using debugger and found out that EEPROM (address 0x51 on our board) has been successfully read, all parameters were sane and SDRAM registers have been updated accordantly. However sdram0_mcsts register's most significant bit never becomes 1, meaning SDRAM controller cannot complete memory initialization and code stays in endless loop:
/* * wait for SDRAM_CFG0_DC_EN to complete */ while (1) { mfsdram(mem_mcsts, mcsts); if ((mcsts & SDRAM_MCSTS_MRSC) != 0) { break; } }
That looks like HW problem for me. Of course, I'll look through actual registers' values more carefully - may be spd_sdram() just parsed EEPROM parameters wrongly but I doubt that.
Just in case - did you happen to have BDI config file for that board - brief search in the ftp://ftp.denx.de/pub/BDI2000/ directory didn't provide results.
Best regards, Leonid.