The V4 and V5 controllers have quite varied register layouts. Inherit the register offsets and naming from the Linux driver. More version specific offsets can be inherited from Linux as needed.
Fixes: 364c22a ("mmc: msm_sdhci: Add SDCC version 5.0.0 support") Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/mmc/msm_sdhci.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 059cb3da77c5..f23d425144ef 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -32,11 +32,8 @@ #define SDCC_MCI_STATUS2 0x6C #define SDCC_MCI_STATUS2_MCI_ACT 0x1 #define SDCC_MCI_HC_MODE 0x78
-/* Non standard (?) SDHCI register */ -#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c - struct msm_sdhc_plat { struct mmc_config cfg; struct mmc mmc; }; @@ -48,8 +45,10 @@ struct msm_sdhc { };
struct msm_sdhc_variant_info { bool mci_removed; + + u32 core_vendor_spec_capabilities0; };
DECLARE_GLOBAL_DATA_PTR;
@@ -180,9 +179,9 @@ static int msm_sdc_probe(struct udevice *dev) */ if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { caps = readl(host->ioaddr + SDHCI_CAPABILITIES); caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; - writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); + writel(caps, host->ioaddr + var_info->core_vendor_spec_capabilities0); }
ret = mmc_of_parse(dev, &plat->cfg); if (ret) @@ -243,12 +242,16 @@ static int msm_sdc_bind(struct udevice *dev) }
static const struct msm_sdhc_variant_info msm_sdhc_mci_var = { .mci_removed = false, + + .core_vendor_spec_capabilities0 = 0x21c, };
static const struct msm_sdhc_variant_info msm_sdhc_v5_var = { .mci_removed = true, + + .core_vendor_spec_capabilities0 = 0x11c, };
static const struct udevice_id msm_mmc_ids[] = { { .compatible = "qcom,sdhci-msm-v4", .data = (ulong)&msm_sdhc_mci_var },