The UART of MT7628 has fixed 40MHz input clock so there is no need to put clock-frequency in every dts files. Just put it into the common dtsi file.
Reviewed-by: Stefan Roese sr@denx.de Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- arch/mips/dts/gardena-smart-gateway-mt7688.dts | 1 - arch/mips/dts/linkit-smart-7688.dts | 1 - arch/mips/dts/mt7628a.dtsi | 6 ++++++ 3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/arch/mips/dts/gardena-smart-gateway-mt7688.dts index eedde89dfd..95675a3947 100644 --- a/arch/mips/dts/gardena-smart-gateway-mt7688.dts +++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts @@ -87,7 +87,6 @@
&uart0 { status = "okay"; - clock-frequency = <40000000>; };
&spi0 { diff --git a/arch/mips/dts/linkit-smart-7688.dts b/arch/mips/dts/linkit-smart-7688.dts index bb10402174..935315743c 100644 --- a/arch/mips/dts/linkit-smart-7688.dts +++ b/arch/mips/dts/linkit-smart-7688.dts @@ -28,7 +28,6 @@
&uart2 { status = "okay"; - clock-frequency = <40000000>; };
&spi0 { diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 1e7d0a6ec5..6bc0722b07 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -127,6 +127,8 @@ compatible = "ns16550a"; reg = <0xc00 0x100>;
+ clock-frequency = <40000000>; + resets = <&resetc 12>; reset-names = "uart0";
@@ -140,6 +142,8 @@ compatible = "ns16550a"; reg = <0xd00 0x100>;
+ clock-frequency = <40000000>; + resets = <&resetc 19>; reset-names = "uart1";
@@ -153,6 +157,8 @@ compatible = "ns16550a"; reg = <0xe00 0x100>;
+ clock-frequency = <40000000>; + resets = <&resetc 20>; reset-names = "uart2";