From: Wojciech Tatarski wtatarski@antmicro.com
According to Zynq Ultrascale TRM all the data transfers are word aligned. So there is no reason to round up size of DMA transfer to ARCH_DMA_MINALIGN (0x40)
Signed-off-by: Wojciech Tatarski wtatarski@antmicro.com Signed-off-by: Tomasz Gorochowik tgorochowik@antmicro.com Tested-by: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@xilinx.com ---
drivers/spi/zynqmp_gqspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 3e0dbb2c7b..81c5e2b22f 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -530,10 +530,10 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
writel((unsigned long)buf, &dma_regs->dmadst); - writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize); + writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize); writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); addr = (unsigned long)buf; - size = roundup(priv->len, ARCH_DMA_MINALIGN); + size = roundup(priv->len, GQSPI_DMA_ALIGN); flush_dcache_range(addr, addr + size);
while (priv->len) { -- 2.17.1
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