Re: [PATCH 1/4] rockchip: rk3588: Sync device tree from linux maintainer tree

On 2023/10/11 06:23, Jonas Karlman wrote:

Sync rk3588 device tree from linux maintainer tree (v6.7-armsoc/dts64). Adds PCIe nodes to rk3588-evb1-v10 and rk3588-rock-5b boards. Also remove includes from u-boot.dtsi-files that is no longer needed.

Linux commits: 42145b7a8235 ("arm64: dts: rockchip: add PCIe network controller to rock-5b") 199cbd5f195a ("arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b") da447ec38780 ("arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b") 86a2024d95e2 ("arm64: dts: rockchip: add PCIe2 network controller to rk3588-evb1") 46bb398ea1d8 ("arm64: dts: rockchip: add PCIe3 bus to rk3588-evb1") 1c9a53ff7ece ("arm64: dts: rockchip: Add sdio node to rock-5b") 3eaf2abd11aa ("arm64: dts: rockchip: Add sfc node to rk3588s") bf012368bb0a ("arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s") 3d77a3e51b0f ("arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s")

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi | 11 +- arch/arm/dts/rk3588-evb1-v10.dts | 98 ++++++++++++++++ arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 60 ---------- arch/arm/dts/rk3588-rock-5b.dts | 140 +++++++++++++++++++++++ arch/arm/dts/rk3588-u-boot.dtsi | 1 - arch/arm/dts/rk3588s-pinctrl.dtsi | 44 +++++++ arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 4 - arch/arm/dts/rk3588s-u-boot.dtsi | 10 -- arch/arm/dts/rk3588s.dtsi | 11 ++ 9 files changed, 294 insertions(+), 85 deletions(-)

diff --git a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi index bd2e25948633..e8566785e965 100644 --- a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi +++ b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi @@ -6,16 +6,7 @@ #include "rk3588-u-boot.dtsi"

/ {

• aliases {

• mmc0 = &sdmmc;
  

• mmc1 = &sdhci;
  

• };
• chosen {

• u-boot,spl-boot-order = &sdhci;
  

• u-boot,spl-boot-order = "same-as-spl", &sdhci;
  

  }; };

-&sdhci {

• bootph-all;

-}; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts index 229a9111f5eb..c3fe58e39e99 100644 --- a/arch/arm/dts/rk3588-evb1-v10.dts +++ b/arch/arm/dts/rk3588-evb1-v10.dts @@ -29,6 +29,46 @@ pwms = <&pwm2 0 25000 0>; };

• pcie20_avdd0v85: pcie20-avdd0v85-regulator {

• compatible = "regulator-fixed";
  

• regulator-name = "pcie20_avdd0v85";
  

• regulator-always-on;
  

• regulator-boot-on;
  

• regulator-min-microvolt = <850000>;
  

• regulator-max-microvolt = <850000>;
  

• vin-supply = <&avdd_0v85_s0>;
  

• };
• pcie20_avdd1v8: pcie20-avdd1v8-regulator {

• compatible = "regulator-fixed";
  

• regulator-name = "pcie20_avdd1v8";
  

• regulator-always-on;
  

• regulator-boot-on;
  

• regulator-min-microvolt = <1800000>;
  

• regulator-max-microvolt = <1800000>;
  

• vin-supply = <&avcc_1v8_s0>;
  

• };
• pcie30_avdd0v75: pcie30-avdd0v75-regulator {

• compatible = "regulator-fixed";
  

• regulator-name = "pcie30_avdd0v75";
  

• regulator-always-on;
  

• regulator-boot-on;
  

• regulator-min-microvolt = <750000>;
  

• regulator-max-microvolt = <750000>;
  

• vin-supply = <&avdd_0v75_s0>;
  

• };
• pcie30_avdd1v8: pcie30-avdd1v8-regulator {

• compatible = "regulator-fixed";
  

• regulator-name = "pcie30_avdd1v8";
  

• regulator-always-on;
  

• regulator-boot-on;
  

• regulator-min-microvolt = <1800000>;
  

• regulator-max-microvolt = <1800000>;
  

• vin-supply = <&avcc_1v8_s0>;
  

• };
• vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin";

@@ -38,6 +78,19 @@ regulator-max-microvolt = <12000000>; };

• vcc3v3_pcie30: vcc3v3-pcie30-regulator {

• compatible = "regulator-fixed";
  

• regulator-name = "vcc3v3_pcie30";
  

• regulator-min-microvolt = <3300000>;
  

• regulator-max-microvolt = <3300000>;
  

• enable-active-high;
  

• gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
  

• startup-delay-us = <5000>;
  

• vin-supply = <&vcc12v_dcin>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&vcc3v3_pcie30_en>;
  

• };
• vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_host";

@@ -87,6 +140,10 @@ status = "okay"; };

+&combphy2_psu {

• status = "okay";

+};

• &cpu_b0 { cpu-supply = <&vdd_cpu_big0_s0>; };

@@ -163,7 +220,32 @@ }; };

+&pcie2x1l1 {

• reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
• pinctrl-names = "default";
• pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>;
• status = "okay";

+};

+&pcie30phy {

• status = "okay";

+};

+&pcie3x4 {

• pinctrl-names = "default";
• pinctrl-0 = <&pcie3_reset>;
• reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
• vpcie3v3-supply = <&vcc3v3_pcie30>;
• status = "okay";

+};

• &pinctrl {
• rtl8111 {

• rtl8111_isolate: rtl8111-isolate {
  

• 	rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
  

• };
  

• };
• rtl8211f { rtl8211f_rst: rtl8211f-rst { rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;

@@ -177,6 +259,22 @@ }; };

• pcie2 {

• pcie2_1_rst: pcie2-1-rst {
  

• 	rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• };
• pcie3 {

• pcie3_reset: pcie3-reset {
  

• 	rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• vcc3v3_pcie30_en: vcc3v3-pcie30-en {
  

• 	rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• };
• usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 96cc84e5aac9..3f390ef26a3f 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -4,9 +4,6 @@ */

#include "rk3588-u-boot.dtsi" -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/usb/pd.h>

/ { @@ -23,19 +20,6 @@ regulator-max-microvolt = <12000000>; };

• vcc3v3_pcie30: vcc3v3-pcie30-regulator {

• compatible = "regulator-fixed";
  

• regulator-name = "vcc3v3_pcie30";
  

• regulator-min-microvolt = <3300000>;
  

• regulator-max-microvolt = <3300000>;
  

• enable-active-high;
  

• gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
  

• startup-delay-us = <5000>;
  

• vin-supply = <&vcc5v0_sys>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&pcie3_vcc3v3_en>;
  

• };
• vcc5v0_usbdcin: vcc5v0-usbdcin { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usbdcin";

@@ -69,53 +53,11 @@ }; };

-&combphy0_ps {

• status = "okay";

-};

• &fspim2_pins { bootph-all; };

-&pcie2x1l2 {

• pinctrl-names = "default";
• pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;
• reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
• status = "okay";

-};

-&pcie30phy {

• status = "okay";

-};

-&pcie3x4 {

• reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
• vpcie3v3-supply = <&vcc3v3_pcie30>;
• pinctrl-names = "default";
• pinctrl-0 = <&pcie3_rst>;
• status = "okay";

-};

• &pinctrl {
• pcie {

• pcie_reset_h: pcie-reset-h {
  

• 	rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• pcie2x1l2_pins: pcie2x1l2-pins {
  

• 	rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
  

• 			<3 RK_PD0 4 &pcfg_pull_none>;
  

• };
  

• pcie3_rst: pcie3-rst {
  

• 	rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• pcie3_vcc3v3_en: pcie3-vcc3v3-en {
  

• 	rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• };
• usb-typec { usbc0_int: usbc0-int { rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;

@@ -138,8 +80,6 @@ u-boot,spl-sfc-no-dma; pinctrl-names = "default"; pinctrl-0 = <&fspim2_pins>;

• #address-cells = <1>;

• #size-cells = <0>; status = "okay";

  flash@0 {

diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts index 8ab60968f275..8618887899d9 100644 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -12,6 +12,7 @@ aliases { mmc0 = &sdhci; mmc1 = &sdmmc;

• mmc2 = &sdio;
  

  serial2 = &uart2; };

@@ -44,6 +45,43 @@ #cooling-cells = <2>; };

• vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {

• compatible = "regulator-fixed";
  

• enable-active-high;
  

• gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&pcie2_0_vcc3v3_en>;
  

• regulator-name = "vcc3v3_pcie2x1l0";
  

• regulator-always-on;
  

• regulator-boot-on;
  

• regulator-min-microvolt = <3300000>;
  

• regulator-max-microvolt = <3300000>;
  

• startup-delay-us = <50000>;
  

• vin-supply = <&vcc5v0_sys>;
  

• };
• vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {

• compatible = "regulator-fixed";
  

• regulator-name = "vcc3v3_pcie2x1l2";
  

• regulator-min-microvolt = <3300000>;
  

• regulator-max-microvolt = <3300000>;
  

• startup-delay-us = <5000>;
  

• vin-supply = <&vcc_3v3_s3>;
  

• };
• vcc3v3_pcie30: vcc3v3-pcie30-regulator {

• compatible = "regulator-fixed";
  

• enable-active-high;
  

• gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&pcie3_vcc3v3_en>;
  

• regulator-name = "vcc3v3_pcie30";
  

• regulator-min-microvolt = <3300000>;
  

• regulator-max-microvolt = <3300000>;
  

• startup-delay-us = <5000>;
  

• vin-supply = <&vcc5v0_sys>;
  

• };
• vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_host";

@@ -76,6 +114,29 @@ regulator-max-microvolt = <1100000>; vin-supply = <&vcc5v0_sys>; };

• vcc3v3_wf: vcc3v3-wf-regulator {

• compatible = "regulator-fixed";
  

• regulator-name = "vcc3v3_wf";
  

• regulator-always-on;
  

• regulator-boot-on;
  

• regulator-min-microvolt = <3300000>;
  

• regulator-max-microvolt = <3300000>;
  

• enable-active-high;
  

• gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&vcc3v3_wf_en>;
  

• startup-delay-us = <50000>;
  

• vin-supply = <&vcc5v0_sys>;
  

• };

+};

+&combphy0_ps {

• status = "okay";

+};

+&combphy1_ps {

• status = "okay"; };

  &cpu_b0 {

@@ -204,6 +265,34 @@ }; };

+&pcie2x1l0 {

• pinctrl-names = "default";
• pinctrl-0 = <&pcie2_0_rst>;
• reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
• vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
• status = "okay";

+};

+&pcie2x1l2 {

• pinctrl-names = "default";
• pinctrl-0 = <&pcie2_2_rst>;
• reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
• vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
• status = "okay";

+};

+&pcie30phy {

• status = "okay";

+};

+&pcie3x4 {

• pinctrl-names = "default";
• pinctrl-0 = <&pcie3_rst>;
• reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
• vpcie3v3-supply = <&vcc3v3_pcie30>;
• status = "okay";

+};

• &pinctrl { hym8563 { hym8563_int: hym8563-int {

@@ -217,11 +306,41 @@ }; };

• pcie2 {

• pcie2_0_rst: pcie2-0-rst {
  

• 	rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
  

• 	rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• pcie2_2_rst: pcie2-2-rst {
  

• 	rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• };

• pcie3 {

• pcie3_rst: pcie3-rst {
  

• 	rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• pcie3_vcc3v3_en: pcie3-vcc3v3-en {
  

• 	rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• };

• usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; };

• m2e {

• vcc3v3_wf_en: vcc3v3-wf-en {
  

• 	rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
  

• };
  

• }; };

  &pwm1 {

@@ -258,6 +377,27 @@ status = "okay"; };

+&sdio {

• max-frequency = <200000000>;
• no-sd;
• no-mmc;
• non-removable;
• bus-width = <4>;
• cap-sdio-irq;
• disable-wp;
• keep-power-in-suspend;
• wakeup-source;
• sd-uhs-sdr12;
• sd-uhs-sdr25;
• sd-uhs-sdr50;
• sd-uhs-sdr104;
• vmmc-supply = <&vcc3v3_wf>;
• vqmmc-supply = <&vcc_1v8_s3>;
• pinctrl-names = "default";
• pinctrl-0 = <&sdiom0_pins>;
• status = "okay";

+};

• &spi2 { status = "okay"; assigned-clocks = <&cru CLK_SPI2>;

diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 68b419f3abd5..15de4706254e 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -3,7 +3,6 @@

• Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.

*/

-#include "rockchip-u-boot.dtsi" #include "rk3588s-u-boot.dtsi"

/ { diff --git a/arch/arm/dts/rk3588s-pinctrl.dtsi b/arch/arm/dts/rk3588s-pinctrl.dtsi index 48181671eacb..63151d9d2377 100644 --- a/arch/arm/dts/rk3588s-pinctrl.dtsi +++ b/arch/arm/dts/rk3588s-pinctrl.dtsi @@ -1349,6 +1349,41 @@ };

i2s2 {

• /omit-if-no-ref/
  

• i2s2m0_lrck: i2s2m0-lrck {
  

• 	rockchip,pins =
  

• 		/* i2s2m0_lrck */
  

• 		<2 RK_PC0 2 &pcfg_pull_none>;
  

• };
  

• /omit-if-no-ref/
  

• i2s2m0_mclk: i2s2m0-mclk {
  

• 	rockchip,pins =
  

• 		/* i2s2m0_mclk */
  

• 		<2 RK_PB6 2 &pcfg_pull_none>;
  

• };
  

• /omit-if-no-ref/
  

• i2s2m0_sclk: i2s2m0-sclk {
  

• 	rockchip,pins =
  

• 		/* i2s2m0_sclk */
  

• 		<2 RK_PB7 2 &pcfg_pull_none>;
  

• };
  

• /omit-if-no-ref/
  

• i2s2m0_sdi: i2s2m0-sdi {
  

• 	rockchip,pins =
  

• 		/* i2s2m0_sdi */
  

• 		<2 RK_PC3 2 &pcfg_pull_none>;
  

• };
  

• /omit-if-no-ref/
  

• i2s2m0_sdo: i2s2m0-sdo {
  

• 	rockchip,pins =
  

• 		/* i2s2m0_sdo */
  

• 		<4 RK_PC3 2 &pcfg_pull_none>;
  

• };
  

• /omit-if-no-ref/ i2s2m1_lrck: i2s2m1-lrck { rockchip,pins =

@@ -3307,6 +3342,15 @@ };

uart9 {

• /omit-if-no-ref/
  

• uart9m0_xfer: uart9m0-xfer {
  

• 	rockchip,pins =
  

• 		/* uart9_rx_m0 */
  

• 		<2 RK_PC4 10 &pcfg_pull_up>,
  

• 		/* uart9_tx_m0 */
  

• 		<2 RK_PC2 10 &pcfg_pull_up>;
  

• };
  

• /omit-if-no-ref/ uart9m1_xfer: uart9m1-xfer { rockchip,pins =

diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi index c47b0a7112c8..584476f77b13 100644 --- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -4,10 +4,6 @@ */

#include "rk3588s-u-boot.dtsi" -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/usb/pd.h>

/ { chosen { diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 27b2d7eff87b..878936fa07d6 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -4,7 +4,6 @@ */

#include "rockchip-u-boot.dtsi" -#include <dt-bindings/phy/phy.h>

/ { aliases { @@ -102,15 +101,6 @@ reg = <0x0 0xfd5c8000 0x0 0x4000>; };

• sfc: spi@fe2b0000 {

• compatible = "rockchip,sfc";
  

• reg = <0x0 0xfe2b0000 0x0 0x4000>;
  

• interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
  

• clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
  

• clock-names = "clk_sfc", "hclk_sfc";
  

• status = "disabled";
  

• };
• rng: rng@fe378000 { compatible = "rockchip,trngv1"; reg = <0x0 0xfe378000 0x0 0x200>;

diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index 5544f66c6ff4..1a820a5a51eb 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -1424,6 +1424,17 @@ }; };

• sfc: spi@fe2b0000 {

• compatible = "rockchip,sfc";
  

• reg = <0x0 0xfe2b0000 0x0 0x4000>;
  

• interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
  

• clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
  

• clock-names = "clk_sfc", "hclk_sfc";
  

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• status = "disabled";
  

• };
• sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>;