This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.
Signed-off-by: Simon Glass sjg@chromium.org ---
board/Marvell/db-mv784mp-gp/MAINTAINERS | 6 - board/Marvell/db-mv784mp-gp/Makefile | 5 - board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 117 -------------------- configs/db-mv784mp-gp_defconfig | 64 ----------- include/configs/db-mv784mp-gp.h | 99 ----------------- 5 files changed, 291 deletions(-) delete mode 100644 board/Marvell/db-mv784mp-gp/MAINTAINERS delete mode 100644 board/Marvell/db-mv784mp-gp/Makefile delete mode 100644 board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c delete mode 100644 configs/db-mv784mp-gp_defconfig delete mode 100644 include/configs/db-mv784mp-gp.h
diff --git a/board/Marvell/db-mv784mp-gp/MAINTAINERS b/board/Marvell/db-mv784mp-gp/MAINTAINERS deleted file mode 100644 index a095f898d40..00000000000 --- a/board/Marvell/db-mv784mp-gp/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DB_MV784MP_GP BOARD -M: Stefan Roese sr@denx.de -S: Maintained -F: board/Marvell/db-mv784mp-gp/ -F: include/configs/db-mv784mp-gp.h -F: configs/db-mv784mp-gp_defconfig diff --git a/board/Marvell/db-mv784mp-gp/Makefile b/board/Marvell/db-mv784mp-gp/Makefile deleted file mode 100644 index 1bd2388afb3..00000000000 --- a/board/Marvell/db-mv784mp-gp/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2014 Stefan Roese sr@denx.de - -obj-y := db-mv784mp-gp.o diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c deleted file mode 100644 index 604e8c1670b..00000000000 --- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Stefan Roese sr@denx.de - */ - -#include <common.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define ETH_PHY_CTRL_REG 0 -#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 -#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) - -/* - * Those values and defines are taken from the Marvell U-Boot version - * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka - * "RD-AXP-GP rev 1.0". - * - * GPPs - * MPP# NAME IN/OUT - * ---------------------------------------------- - * 21 SW_Reset_ OUT - * 25 Phy_Int# IN - * 28 SDI_WP IN - * 29 SDI_Status IN - * 54-61 On GPP Connector ? - * 62 Switch Interrupt IN - * 63-65 Reserved from SW Board ? - * 66 SW_BRD connected IN - */ -#define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20))) -#define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27))) -#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0)) - -#define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20)) -#define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27)) -#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0 - -int board_early_init_f(void) -{ - /* Configure MPP */ - writel(0x00000000, MVEBU_MPP_BASE + 0x00); - writel(0x00000000, MVEBU_MPP_BASE + 0x04); - writel(0x33000000, MVEBU_MPP_BASE + 0x08); - writel(0x11000000, MVEBU_MPP_BASE + 0x0c); - writel(0x11111111, MVEBU_MPP_BASE + 0x10); - writel(0x00221100, MVEBU_MPP_BASE + 0x14); - writel(0x00000003, MVEBU_MPP_BASE + 0x18); - writel(0x00000000, MVEBU_MPP_BASE + 0x1c); - writel(0x00000000, MVEBU_MPP_BASE + 0x20); - - /* Configure GPIO */ - writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); - writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); - writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); - writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); - writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); - writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -int checkboard(void) -{ - puts("Board: Marvell DB-MV784MP-GP\n"); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in controller(s) come first */ - return pci_eth_init(bis); -} - -int board_phy_config(struct phy_device *phydev) -{ - u16 reg; - - /* Enable QSGMII AN */ - /* Set page to 4 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4); - /* Enable AN */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140); - /* Set page to 0 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0); - - /* Phy C_ANEG */ - reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4); - reg |= 0x1E0; - phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg); - - /* Soft-Reset */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); - phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); - - /* Power up the phy */ - reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG); - reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK); - phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg); - - printf("88E1545 Initialized\n"); - return 0; -} diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig deleted file mode 100644 index 3f140986b69..00000000000 --- a/configs/db-mv784mp-gp_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MVEBU=y -CONFIG_SYS_TEXT_BASE=0x00800000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_DB_MV784MP_GP=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 -CONFIG_DEBUG_UART_CLOCK=250000000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_DEBUG_UART=y -CONFIG_NR_DRAM_BANKS=2 -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_BOOTDELAY=3 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set -# CONFIG_SPL_PARTITION_UUIDS is not set -CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" -CONFIG_SPL_OF_TRANSLATE=y -CONFIG_SATA_MV=y -# CONFIG_MMC is not set -CONFIG_NAND=y -CONFIG_NAND_PXA3XX=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_GIGE=y -CONFIG_MVNETA=y -CONFIG_MII=y -CONFIG_PCI=y -CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYS_NS16550=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h deleted file mode 100644 index 8ad007cc491..00000000000 --- a/include/configs/db-mv784mp-gp.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014-2015 Stefan Roese sr@denx.de - */ - -#ifndef _CONFIG_DB_MV7846MP_GP_H -#define _CONFIG_DB_MV7846MP_GP_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_DB_784MP_GP /* Board target name for DDR training */ - -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 - -/* SPI NOR flash default params, used by sf commands */ -#define CONFIG_SF_DEFAULT_SPEED 1000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* SATA support */ -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LBA48 - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_MVEBU -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* NAND */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Memory layout while starting into the bin_hdr via the - * BootROM: - * - * 0x4000.4000 - 0x4003.4000 headers space (192KiB) - * 0x4000.4030 bin_hdr start address - * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) - * 0x4007.fffc BootROM stack top - * - * The address space between 0x4007.fffc and 0x400f.fff is not locked in - * L2 cache thus cannot be used. - */ - -/* SPL */ -/* Defines for SPL */ -#define CONFIG_SPL_TEXT_BASE 0x40004030 -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -/* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS - -/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SPD_EEPROM 0x4e -#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ - -#endif /* _CONFIG_DB_MV7846MP_GP_H */