On Wed, 2016-01-13 at 03:34 +0100, Marek Vasut wrote:
On Wednesday, January 13, 2016 at 03:23:38 AM, Chin Liang See wrote:
On Wed, 2016-01-13 at 03:07 +0100, Marek Vasut wrote:
On Wednesday, January 13, 2016 at 03:05:40 AM, Chin Liang See wrote:
On Tue, 2016-01-12 at 03:48 +0100, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 01:50:18 AM, Chin Liang See
wrote:
On Tue, 2016-01-12 at 01:31 +0100, Marek Vasut wrote: > On Tuesday, January 12, 2016 at 01:26:58 AM, Chin Liang > See > > wrote: > > On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen > > wrote: [...]
> btw. Completely off-topic, but is there any chance altera > will > release the > algorithm to compute these magic values which are in the > header > files > from > the base values inserted into the HPS component in QSys ?
I would not suggesting that as Qsys and Quartus are doing heavylifting tasks there. The value would depends on the options being choosed, device type, device revision (if any). They also being patched from time to time too.
Is it all really _that_ complicated ? That's why I'd like to see the code that's doing all that computation.
Actually more challenges is that the code is proprietary. We might get stopped by legal team before making this happen too.
What's proprietary about it ? Isn't that SDRAM controller made in -house by Altera ?
Oh seems we might discussing slightly different things. I am referring to IOCSR which is the bitstream for setting up the IO buffers. I presume you are referring to SDRAM configuration, right?
Yeah, I'm talking about the SDRAM controller configuration values.
Cool, let me take a look on the SDRAM handoff we have today.
I know the IOCSR is a problem. I am reverse engineering the Cyclone IV bitstream format in my free time now and then, but I didn't have time to look at C V and I don't plan to do it any soon. I think even my C/IV activity might trigger someone in Altera once I get around to releasing it ;-)
haha :) There are various knob in Quartus that might change the IOCSR itself. Shall let the tools to handle it for better user experience.
Even if it's done at compile-time, it'd still be better than the horrible headers which we have to use now.
I believe DTS would be better format than header file.
Coming up with sensible bindings would be hard though.
Yah, that why this is get rid when we switch to Arria 10 SoC :)
Well you'll still need to configure the HardIP which does the DDR calib with some DDR config values, so you cannot get rid of it entirely. Unless you pull these values from SPD, which I doubt would be the case, since the A10 would be mostly embedded chip.
Nope, its part of bitstream. Bitstream will contain the information on the DDR devices on the board. This is similar to what being implemented in traditional FPGA devices.
Thanks Chin Liang
Best regards, Marek Vasut