From d5940c0f96ed6ca380cba1c4968d1aeee0b29782 Mon Sep 17 00:00:00 2001
From: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Date: Tue, 14 Aug 2007 05:48:58 -0500
Subject: [PATCH] ColdFire MCF52x2: Header files update 3

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
---
 include/asm-m68k/m5271.h |  100 +++++++++++++++++++++
 include/asm-m68k/m5272.h |  218 ++++++++++++++++++++++++++++++++++------------
 include/asm-m68k/m5282.h |   94 ++++++++++++++++++++-
 3 files changed, 356 insertions(+), 56 deletions(-)

diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h
index e0f02cf..f154cca 100644
--- a/include/asm-m68k/m5271.h
+++ b/include/asm-m68k/m5271.h
@@ -117,4 +117,104 @@
 
 #define MCFSIM_ICR1				0x000C41
 
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_SCM			(8)
+#define INT0_LO_DMA0			(9)
+#define INT0_LO_DMA1			(10)
+#define INT0_LO_DMA2			(11)
+#define INT0_LO_DMA3			(12)
+#define INT0_LO_UART0			(13)
+#define INT0_LO_UART1			(14)
+#define INT0_LO_UART2			(15)
+#define INT0_LO_RSVD1			(16)
+#define INT0_LO_I2C			(17)
+#define INT0_LO_QSPI			(18)
+#define INT0_LO_DTMR0			(19)
+#define INT0_LO_DTMR1			(20)
+#define INT0_LO_DTMR2			(21)
+#define INT0_LO_DTMR3			(22)
+#define INT0_LO_FEC_TXF			(23)
+#define INT0_LO_FEC_TXB			(24)
+#define INT0_LO_FEC_UN			(25)
+#define INT0_LO_FEC_RL			(26)
+#define INT0_LO_FEC_RXF			(27)
+#define INT0_LO_FEC_RXB			(28)
+#define INT0_LO_FEC_MII			(29)
+#define INT0_LO_FEC_LC			(30)
+#define INT0_LO_FEC_HBERR		(31)
+#define INT0_HI_FEC_GRA			(32)
+#define INT0_HI_FEC_EBERR		(33)
+#define INT0_HI_FEC_BABT		(34)
+#define INT0_HI_FEC_BABR		(35)
+#define INT0_HI_PIT0			(36)
+#define INT0_HI_PIT1			(37)
+#define INT0_HI_PIT2			(38)
+#define INT0_HI_PIT3			(39)
+#define INT0_HI_RNG			(40)
+#define INT0_HI_SKHA			(41)
+#define INT0_HI_MDHA			(42)
+#define INT0_HI_CAN1_BUF0I		(43)
+#define INT0_HI_CAN1_BUF1I		(44)
+#define INT0_HI_CAN1_BUF2I		(45)
+#define INT0_HI_CAN1_BUF3I		(46)
+#define INT0_HI_CAN1_BUF4I		(47)
+#define INT0_HI_CAN1_BUF5I		(48)
+#define INT0_HI_CAN1_BUF6I		(49)
+#define INT0_HI_CAN1_BUF7I		(50)
+#define INT0_HI_CAN1_BUF8I		(51)
+#define INT0_HI_CAN1_BUF9I		(52)
+#define INT0_HI_CAN1_BUF10I		(53)
+#define INT0_HI_CAN1_BUF11I		(54)
+#define INT0_HI_CAN1_BUF12I		(55)
+#define INT0_HI_CAN1_BUF13I		(56)
+#define INT0_HI_CAN1_BUF14I		(57)
+#define INT0_HI_CAN1_BUF15I		(58)
+#define INT0_HI_CAN1_ERRINT		(59)
+#define INT0_HI_CAN1_BOFFINT		(60)
+/* 60-63 Reserved */
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31			(0x80000000)
+#define INTC_IPRL_INT30			(0x40000000)
+#define INTC_IPRL_INT29			(0x20000000)
+#define INTC_IPRL_INT28			(0x10000000)
+#define INTC_IPRL_INT27			(0x08000000)
+#define INTC_IPRL_INT26			(0x04000000)
+#define INTC_IPRL_INT25			(0x02000000)
+#define INTC_IPRL_INT24			(0x01000000)
+#define INTC_IPRL_INT23			(0x00800000)
+#define INTC_IPRL_INT22			(0x00400000)
+#define INTC_IPRL_INT21			(0x00200000)
+#define INTC_IPRL_INT20			(0x00100000)
+#define INTC_IPRL_INT19			(0x00080000)
+#define INTC_IPRL_INT18			(0x00040000)
+#define INTC_IPRL_INT17			(0x00020000)
+#define INTC_IPRL_INT16			(0x00010000)
+#define INTC_IPRL_INT15			(0x00008000)
+#define INTC_IPRL_INT14			(0x00004000)
+#define INTC_IPRL_INT13			(0x00002000)
+#define INTC_IPRL_INT12			(0x00001000)
+#define INTC_IPRL_INT11			(0x00000800)
+#define INTC_IPRL_INT10			(0x00000400)
+#define INTC_IPRL_INT9			(0x00000200)
+#define INTC_IPRL_INT8			(0x00000100)
+#define INTC_IPRL_INT7			(0x00000080)
+#define INTC_IPRL_INT6			(0x00000040)
+#define INTC_IPRL_INT5			(0x00000020)
+#define INTC_IPRL_INT4			(0x00000010)
+#define INTC_IPRL_INT3			(0x00000008)
+#define INTC_IPRL_INT2			(0x00000004)
+#define INTC_IPRL_INT1			(0x00000002)
+#define INTC_IPRL_INT0			(0x00000001)
+
 #endif	/* _MCF5271_H_ */
diff --git a/include/asm-m68k/m5272.h b/include/asm-m68k/m5272.h
index 54d4a32..f193c22 100644
--- a/include/asm-m68k/m5272.h
+++ b/include/asm-m68k/m5272.h
@@ -35,65 +35,173 @@
 
 #define INT_RAM_SIZE 4096
 
+#define GPIO_PACNT_PA15MSK		(0xC0000000)
+#define GPIO_PACNT_DGNT1		(0x40000000)
+#define GPIO_PACNT_PA14MSK		(0x30000000)
+#define GPIO_PACNT_DREQ1		(0x10000000)
+#define GPIO_PACNT_PA13MSK		(0x0C000000)
+#define GPIO_PACNT_DFSC3		(0x04000000)
+#define GPIO_PACNT_PA12MSK		(0x03000000)
+#define GPIO_PACNT_DFSC2		(0x01000000)
+#define GPIO_PACNT_PA11MSK		(0x00C00000)
+#define GPIO_PACNT_QSPI_CS1		(0x00800000)
+#define GPIO_PACNT_PA10MSK		(0x00300000)
+#define GPIO_PACNT_DREQ0		(0x00100000)
+#define GPIO_PACNT_PA9MSK		(0x000C0000)
+#define GPIO_PACNT_DGNT0		(0x00040000)
+#define GPIO_PACNT_PA8MSK		(0x00030000)
+#define GPIO_PACNT_FSC0			(0x00010000)
+#define GPIO_PACNT_FSR0			(0x00010000)
+#define GPIO_PACNT_PA7MSK		(0x0000C000)
+#define GPIO_PACNT_DOUT3		(0x00008000)
+#define GPIO_PACNT_QSPI_CS3		(0x00004000)
+#define GPIO_PACNT_PA6MSK		(0x00003000)
+#define GPIO_PACNT_USB_RXD		(0x00001000)
+#define GPIO_PACNT_PA5MSK		(0x00000C00)
+#define GPIO_PACNT_USB_TXEN		(0x00000400)
+#define GPIO_PACNT_PA4MSK		(0x00000300)
+#define GPIO_PACNT_USB_SUSP		(0x00000100)
+#define GPIO_PACNT_PA3MSK		(0x000000C0)
+#define GPIO_PACNT_USB_TN		(0x00000040)
+#define GPIO_PACNT_PA2MSK		(0x00000030)
+#define GPIO_PACNT_USB_RN		(0x00000010)
+#define GPIO_PACNT_PA1MSK		(0x0000000C)
+#define GPIO_PACNT_USB_RP		(0x00000004)
+#define GPIO_PACNT_PA0MSK		(0x00000003)
+#define GPIO_PACNT_USB_TP		(0x00000001)
 
-/*
- *	Define the 5272 SIM register set addresses.
- */
-#define	MCFSIM_SCR		0x04		/* SIM Config reg (r/w) */
-#define	MCFSIM_SPR		0x06		/* System Protection reg (r/w)*/
-#define	MCFSIM_PMR		0x08		/* Power Management reg (r/w) */
-#define	MCFSIM_APMR		0x0e		/* Active Low Power reg (r/w) */
-#define	MCFSIM_DIR		0x10		/* Device Identity reg (r/w) */
-
-#define	MCFSIM_ICR1		0x20		/* Intr Ctrl reg 1 (r/w) */
-#define	MCFSIM_ICR2		0x24		/* Intr Ctrl reg 2 (r/w) */
-#define	MCFSIM_ICR3		0x28		/* Intr Ctrl reg 3 (r/w) */
-#define	MCFSIM_ICR4		0x2c		/* Intr Ctrl reg 4 (r/w) */
-
-#define MCFSIM_ISR		0x30		/* Interrupt Source reg (r/w) */
-#define MCFSIM_PITR		0x34		/* Interrupt Transition (r/w) */
-#define	MCFSIM_PIWR		0x38		/* Interrupt Wakeup reg (r/w) */
-#define	MCFSIM_PIVR		0x3f		/* Interrupt Vector reg (r/w( */
+#define GPIO_PBCNT_PB15MSK		(0xC0000000)
+#define GPIO_PBCNT_E_MDC		(0x40000000)
+#define GPIO_PBCNT_PB14MSK		(0x30000000)
+#define GPIO_PBCNT_E_RXER		(0x10000000)
+#define GPIO_PBCNT_PB13MSK		(0x0C000000)
+#define GPIO_PBCNT_E_RXD1		(0x04000000)
+#define GPIO_PBCNT_PB12MSK		(0x03000000)
+#define GPIO_PBCNT_E_RXD2		(0x01000000)
+#define GPIO_PBCNT_PB11MSK		(0x00C00000)
+#define GPIO_PBCNT_E_RXD3		(0x00400000)
+#define GPIO_PBCNT_PB10MSK		(0x00300000)
+#define GPIO_PBCNT_E_TXD1		(0x00100000)
+#define GPIO_PBCNT_PB9MSK		(0x000C0000)
+#define GPIO_PBCNT_E_TXD2		(0x00040000)
+#define GPIO_PBCNT_PB8MSK		(0x00030000)
+#define GPIO_PBCNT_E_TXD3		(0x00010000)
+#define GPIO_PBCNT_PB7MSK		(0x0000C000)
+#define GPIO_PBCNT_TOUT0		(0x00004000)
+#define GPIO_PBCNT_PB6MSK		(0x00003000)
+#define GPIO_PBCNT_TA			(0x00001000)
+#define GPIO_PBCNT_PB4MSK		(0x00000300)
+#define GPIO_PBCNT_URT0_CLK		(0x00000100)
+#define GPIO_PBCNT_PB3MSK		(0x000000C0)
+#define GPIO_PBCNT_URT0_RTS		(0x00000040)
+#define GPIO_PBCNT_PB2MSK		(0x00000030)
+#define GPIO_PBCNT_URT0_CTS		(0x00000010)
+#define GPIO_PBCNT_PB1MSK		(0x0000000C)
+#define GPIO_PBCNT_URT0_RXD		(0x00000004)
+#define GPIO_PBCNT_URT0_TIN2		(0x00000004)
+#define GPIO_PBCNT_PB0MSK		(0x00000003)
+#define GPIO_PBCNT_URT0_TXD		(0x00000001)
 
-#define	MCFSIM_WRRR		0x280		/* Watchdog reference (r/w) */
-#define	MCFSIM_WIRR		0x284		/* Watchdog interrupt (r/w) */
-#define	MCFSIM_WCR		0x288		/* Watchdog counter (r/w) */
-#define	MCFSIM_WER		0x28c		/* Watchdog event (r/w) */
+#define GPIO_PDCNT_PD7MSK		(0x0000C000)
+#define GPIO_PDCNT_TIN1			(0x00008000)
+#define GPIO_PDCNT_PWM_OUT2		(0x00004000)
+#define GPIO_PDCNT_PD6MSK		(0x00003000)
+#define GPIO_PDCNT_TOUT1		(0x00002000)
+#define GPIO_PDCNT_PWM_OUT1		(0x00001000)
+#define GPIO_PDCNT_PD5MSK		(0x00000C00)
+#define GPIO_PDCNT_INT4			(0x00000C00)
+#define GPIO_PDCNT_DIN3			(0x00000800)
+#define GPIO_PDCNT_PD4MSK		(0x00000300)
+#define GPIO_PDCNT_URT1_TXD		(0x00000200)
+#define GPIO_PDCNT_DOUT0		(0x00000100)
+#define GPIO_PDCNT_PD3MSK		(0x000000C0)
+#define GPIO_PDCNT_INT5			(0x000000C0)
+#define GPIO_PDCNT_URT1_RTS		(0x00000080)
+#define GPIO_PDCNT_PD2MSK		(0x00000030)
+#define GPIO_PDCNT_QSPI_CS2		(0x00000030)
+#define GPIO_PDCNT_URT1_CTS		(0x00000020)
+#define GPIO_PDCNT_PD1MSK		(0x0000000C)
+#define GPIO_PDCNT_URT1_RXD		(0x00000008)
+#define GPIO_PDCNT_URT1_TIN3		(0x00000008)
+#define GPIO_PDCNT_DIN0			(0x00000004)
+#define GPIO_PDCNT_PD0MSK		(0x00000003)
+#define GPIO_PDCNT_URT1_CLK		(0x00000002)
+#define GPIO_PDCNT_DCL0			(0x00000001)
 
-#define	MCFSIM_CSBR0		0x40		/* CS0 Base Address (r/w) */
-#define	MCFSIM_CSOR0		0x44		/* CS0 Option (r/w) */
-#define	MCFSIM_CSBR1		0x48		/* CS1 Base Address (r/w) */
-#define	MCFSIM_CSOR1		0x4c		/* CS1 Option (r/w) */
-#define	MCFSIM_CSBR2		0x50		/* CS2 Base Address (r/w) */
-#define	MCFSIM_CSOR2		0x54		/* CS2 Option (r/w) */
-#define	MCFSIM_CSBR3		0x58		/* CS3 Base Address (r/w) */
-#define	MCFSIM_CSOR3		0x5c		/* CS3 Option (r/w) */
-#define	MCFSIM_CSBR4		0x60		/* CS4 Base Address (r/w) */
-#define	MCFSIM_CSOR4		0x64		/* CS4 Option (r/w) */
-#define	MCFSIM_CSBR5		0x68		/* CS5 Base Address (r/w) */
-#define	MCFSIM_CSOR5		0x6c		/* CS5 Option (r/w) */
-#define	MCFSIM_CSBR6		0x70		/* CS6 Base Address (r/w) */
-#define	MCFSIM_CSOR6		0x74		/* CS6 Option (r/w) */
-#define	MCFSIM_CSBR7		0x78		/* CS7 Base Address (r/w) */
-#define	MCFSIM_CSOR7		0x7c		/* CS7 Option (r/w) */
+#define INT_RSVD0			(0)
+#define INT_INT1			(1)
+#define INT_INT2			(2)
+#define INT_INT3			(3)
+#define INT_INT4			(4)
+#define INT_TMR0			(5)
+#define INT_TMR1			(6)
+#define INT_TMR2			(7)
+#define INT_TMR3			(8)
+#define INT_UART1			(9)
+#define INT_UART2			(10)
+#define INT_PLIP			(11)
+#define INT_PLIA			(12)
+#define INT_USB0			(13)
+#define INT_USB1			(14)
+#define INT_USB2			(15)
+#define INT_USB3			(16)
+#define INT_USB4			(17)
+#define INT_USB5			(18)
+#define INT_USB6			(19)
+#define INT_USB7			(20)
+#define INT_DMA				(21)
+#define INT_ERX				(22)
+#define INT_ETX				(23)
+#define INT_ENTC			(24)
+#define INT_QSPI			(25)
+#define INT_INT5			(26)
+#define INT_INT6			(27)
+#define INT_SWTO			(28)
 
-#define	MCFSIM_SDCR		0x180		/* SDRAM Configuration (r/w) */
-#define	MCFSIM_SDTR		0x184		/* SDRAM Timing (r/w) */
-#define	MCFSIM_DCAR0		0x4c		/* DRAM 0 Address reg(r/w) */
-#define	MCFSIM_DCMR0		0x50		/* DRAM 0 Mask reg (r/w) */
-#define	MCFSIM_DCCR0		0x57		/* DRAM 0 Control reg (r/w) */
-#define	MCFSIM_DCAR1		0x58		/* DRAM 1 Address reg (r/w) */
-#define	MCFSIM_DCMR1		0x5c		/* DRAM 1 Mask reg (r/w) */
-#define	MCFSIM_DCCR1		0x63		/* DRAM 1 Control reg (r/w) */
+#define INT_ICR1_TMR0MASK		(0x000F000)
+#define INT_ICR1_TMR0PI			(0x0008000)
+#define INT_ICR1_TMR0IPL(x)		(((x)&0x7)<<12)
+#define INT_ICR1_TMR1MASK		(0x0000F00)
+#define INT_ICR1_TMR1PI			(0x0000800)
+#define INT_ICR1_TMR1IPL(x)		(((x)&0x7)<<8)
+#define INT_ICR1_TMR2MASK		(0x00000F0)
+#define INT_ICR1_TMR2PI			(0x0000080)
+#define INT_ICR1_TMR2IPL(x)		(((x)&0x7)<<4)
+#define INT_ICR1_TMR3MASK		(0x000000F)
+#define INT_ICR1_TMR3PI			(0x0000008)
+#define INT_ICR1_TMR3IPL(x)		(((x)&0x7))
 
-#define	MCFSIM_PACNT		0x80		/* Port A Control (r/w) */
-#define	MCFSIM_PADDR		0x84		/* Port A Direction (r/w) */
-#define	MCFSIM_PADAT		0x86		/* Port A Data (r/w) */
-#define	MCFSIM_PBCNT		0x88		/* Port B Control (r/w) */
-#define	MCFSIM_PBDDR		0x8c		/* Port B Direction (r/w) */
-#define	MCFSIM_PBDAT		0x8e		/* Port B Data (r/w) */
-#define	MCFSIM_PCDDR		0x94		/* Port C Direction (r/w) */
-#define	MCFSIM_PCDAT		0x96		/* Port C Data (r/w) */
-#define	MCFSIM_PDCNT		0x98		/* Port D Control (r/w) */
+#define INT_ISR_INT31			(0x80000000)
+#define INT_ISR_INT30			(0x40000000)
+#define INT_ISR_INT29			(0x20000000)
+#define INT_ISR_INT28			(0x10000000)
+#define INT_ISR_INT27			(0x08000000)
+#define INT_ISR_INT26			(0x04000000)
+#define INT_ISR_INT25			(0x02000000)
+#define INT_ISR_INT24			(0x01000000)
+#define INT_ISR_INT23			(0x00800000)
+#define INT_ISR_INT22			(0x00400000)
+#define INT_ISR_INT21			(0x00200000)
+#define INT_ISR_INT20			(0x00100000)
+#define INT_ISR_INT19			(0x00080000)
+#define INT_ISR_INT18			(0x00040000)
+#define INT_ISR_INT17			(0x00020000)
+#define INT_ISR_INT16			(0x00010000)
+#define INT_ISR_INT15			(0x00008000)
+#define INT_ISR_INT14			(0x00004000)
+#define INT_ISR_INT13			(0x00002000)
+#define INT_ISR_INT12			(0x00001000)
+#define INT_ISR_INT11			(0x00000800)
+#define INT_ISR_INT10			(0x00000400)
+#define INT_ISR_INT9			(0x00000200)
+#define INT_ISR_INT8			(0x00000100)
+#define INT_ISR_INT7			(0x00000080)
+#define INT_ISR_INT6			(0x00000040)
+#define INT_ISR_INT5			(0x00000020)
+#define INT_ISR_INT4			(0x00000010)
+#define INT_ISR_INT3			(0x00000008)
+#define INT_ISR_INT2			(0x00000004)
+#define INT_ISR_INT1			(0x00000002)
+#define INT_ISR_INT0			(0x00000001)
 
 #endif	/* mcf5272_h */
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
index e5058a4..68994b6 100644
--- a/include/asm-m68k/m5282.h
+++ b/include/asm-m68k/m5282.h
@@ -23,7 +23,99 @@
 /****************************************************************************/
 #ifndef	m5282_h
 #define	m5282_h
-/****************************************************************************/
+
+/*********************************************************************
+* PLL Clock Module
+*********************************************************************/
+/* Bit definitions and macros for PLL_SYNCR */
+#define PLL_SYNCR_LOLRE			(0x8000)
+#define PLL_SYNCR_MFD2			(0x4000)
+#define PLL_SYNCR_MFD1			(0x2000)
+#define PLL_SYNCR_MFD0			(0x1000)
+#define PLL_SYNCR_LOCRE			(0x0800)
+#define PLL_SYNCR_RFC2			(0x0400)
+#define PLL_SYNCR_RFC1			(0x0200)
+#define PLL_SYNCR_RFC0			(0x0100)
+#define PLL_SYNCR_LOCEN			(0x0080)
+#define PLL_SYNCR_DISCLK		(0x0040)
+#define PLL_SYNCR_FWKUP			(0x0020)
+#define PLL_SYNCR_STPMD1		(0x0008)
+#define PLL_SYNCR_STPMD0		(0x0004)
+
+/* Bit definitions and macros for PLL_SYNSR */
+#define PLL_SYNSR_MODE			(0x0080)
+#define PLL_SYNSR_PLLSEL		(0x0040)
+#define PLL_SYNSR_PLLREF		(0x0020)
+#define PLL_SYNSR_LOCKS			(0x0010)
+#define PLL_SYNSR_LOCK			(0x0008)
+#define PLL_SYNSR_LOCS			(0x0004)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0				(0)
+#define INT0_LO_EPORT1				(1)
+#define INT0_LO_EPORT2				(2)
+#define INT0_LO_EPORT3				(3)
+#define INT0_LO_EPORT4				(4)
+#define INT0_LO_EPORT5				(5)
+#define INT0_LO_EPORT6				(6)
+#define INT0_LO_EPORT7				(7)
+#define INT0_LO_SCM_SWT1			(8)
+#define INT0_LO_DMA_00				(9)
+#define INT0_LO_DMA_01				(10)
+#define INT0_LO_DMA_02				(11)
+#define INT0_LO_DMA_03				(12)
+#define INT0_LO_UART0				(13)
+#define INT0_LO_UART1				(14)
+#define INT0_LO_UART2				(15)
+#define INT0_LO_RSVD1				(16)
+#define INT0_LO_I2C				(17)
+#define INT0_LO_QSPI				(18)
+#define INT0_LO_DTMR0				(19)
+#define INT0_LO_DTMR1				(20)
+#define INT0_LO_DTMR2				(21)
+#define INT0_LO_DTMR3				(22)
+#define INT0_LO_FEC_TXF				(23)
+#define INT0_LO_FEC_TXB				(24)
+#define INT0_LO_FEC_UN				(25)
+#define INT0_LO_FEC_RL				(26)
+#define INT0_LO_FEC_RXF				(27)
+#define INT0_LO_FEC_RXB				(28)
+#define INT0_LO_FEC_MII				(29)
+#define INT0_LO_FEC_LC				(30)
+#define INT0_LO_FEC_HBERR			(31)
+#define INT0_HI_FEC_GRA				(32)
+#define INT0_HI_FEC_EBERR			(33)
+#define INT0_HI_FEC_BABT			(34)
+#define INT0_HI_FEC_BABR			(35)
+#define INT0_HI_PMM_LVDF			(36)
+#define INT0_HI_QADC_CF1			(37)
+#define INT0_HI_QADC_CF2			(38)
+#define INT0_HI_QADC_PF1			(39)
+#define INT0_HI_QADC_PF2			(40)
+#define INT0_HI_GPTA_TOF			(41)
+#define INT0_HI_GPTA_PAIF			(42)
+#define INT0_HI_GPTA_PAOVF			(43)
+#define INT0_HI_GPTA_C0F			(44)
+#define INT0_HI_GPTA_C1F			(45)
+#define INT0_HI_GPTA_C2F			(46)
+#define INT0_HI_GPTA_C3F			(47)
+#define INT0_HI_GPTB_TOF			(48)
+#define INT0_HI_GPTB_PAIF			(49)
+#define INT0_HI_GPTB_PAOVF			(50)
+#define INT0_HI_GPTB_C0F			(51)
+#define INT0_HI_GPTB_C1F			(52)
+#define INT0_HI_GPTB_C2F			(53)
+#define INT0_HI_GPTB_C3F			(54)
+#define INT0_HI_PIT0				(55)
+#define INT0_HI_PIT1				(56)
+#define INT0_HI_PIT2				(57)
+#define INT0_HI_PIT3				(58)
+#define INT0_HI_CFM_CBEIF			(59)
+#define INT0_HI_CFM_CCIF			(60)
+#define INT0_HI_CFM_PVIF			(61)
+#define INT0_HI_CFM_AEIF			(62)
 
 /*
  * Size of internal RAM
-- 
1.5.2

