On Fri, Jul 09, 2021 at 08:02:03PM +0530, Kishon Vijay Abraham I wrote:
Hi Tom,
On 11/05/21 8:03 pm, Tom Rini wrote:
On Tue, May 11, 2021 at 07:28:10PM +0530, Kishon Vijay Abraham I wrote:
Hi Tom,
On 07/05/21 10:44 pm, Tom Rini wrote:
On Tue, May 04, 2021 at 04:11:54PM +0530, Kishon Vijay Abraham I wrote:
MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1" on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 18.
Signed-off-by: Kishon Vijay Abraham I kishon@ti.com Reviewed-by: Suman Anna s-anna@ti.com
include/configs/j721e_evm.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index b707fc4e89..00d0a18a68 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -139,11 +139,24 @@ #endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
- "do_main_cpsw0_qsgmii_phyinit=1\0" \
When would this be not true?
If the user don't want to use QSGMII, this could be set to false. For instance the SERDES in J7200 can be used such that it can be used with two protocols at a time. So it can be either PCIe + QSGMII or PCIe + USB. So for use cases which require PCIe + USB, this could be set to false.
Then we need to create doc/board/ti/j721e_evm.rst with some general content and then document the above in there.
There is already a document @ board/ti/j721e/README which has some general information. Maybe that could be updated and moved to doc/board/ti/j721e_evm.rst?
Yes, board/*/boardname/README should be converted to doc/board/*/boardname.rst in geneal.